i.MX7ULP: Fix system reset after a7 rtc alarm expired.

The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index d58ed43199e177fe2b61e6802bb1c36346d370c3..3c82e9921ed56fa3d358f47055fa9c8fede37975 100644 (file)
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -58,6 +58,7 @@
 #define USDHC1_AIPS2_SLOT              (56)
 #define RGPIO2P0_AIPS0_SLOT            (15)
 #define RGPIO2P1_AIPS2_SLOT            (15)
+#define SNVS_AIPS2_SLOT                        (35)
 #define IOMUXC0_AIPS0_SLOT             (61)
 #define OCOTP_CTRL_AIPS1_SLOT          (38)
 #define OCOTP_CTRL_PCC1_SLOT           (38)
@@ -177,6 +178,9 @@
 #define USDHC0_RBASE   ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
 #define USDHC1_RBASE   ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
 
+#define SNVS_BASE      ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
+#define SNVS_LP_LPCR   (SNVS_BASE + 0x38)
+
 #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
 #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
 
@@ -939,6 +943,9 @@
 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK      ((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK      ((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
 
+#define SNVS_LPCR_DPEN                         (0x20)
+#define SNVS_LPCR_SRTC_ENV                     (0x1)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 
 #include <asm/types.h>

diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 6015c11869dca7d5103e5ad86016444a536ef8eb..7119ee4a0772c68356c02332f62837fbe7d1ee16 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -106,6 +106,10 @@ void s_init(void)
        /* clock configuration. */
        clock_init();
 
+       if (soc_rev() < CHIP_REV_2_0) {
+               /* enable dumb pmic */
+               writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
+       }
        return;
 }