arm64: zynqmp: Add support for KD240 Kria SOM CC

Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/835f1d1b8982d46b902db69daad64e8445c051e9.1695808407.git.michal.simek@amd.com

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bde2176ec7f6857feb43aad943fd21499711b469..e42261233758e2aa39d50ff7478c7fc74495a272 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
        zynqmp-smk-k24-revA.dtb                 \
        zynqmp-sm-k26-revA.dtb                  \
        zynqmp-smk-k26-revA.dtb                 \
+       zynqmp-sck-kd-g-revA.dtbo               \
        zynqmp-sck-kr-g-revA.dtbo               \
        zynqmp-sck-kr-g-revB.dtbo               \
        zynqmp-sck-kv-g-revA.dtbo               \

diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
new file mode 100644 (file)
index 0000000..5a5c1ef
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KD240 revA Carrier Card
+ *
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+       compatible = "xlnx,zynqmp-sk-kd240-rev1",
+                    "xlnx,zynqmp-sk-kd240-revB",
+                    "xlnx,zynqmp-sk-kd240-revA",
+                    "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
+       model = "ZynqMP KD240 revA/B/1";
+
+       ina260-u3 {
+               compatible = "iio-hwmon";
+               io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
+       };
+
+       clk_26: clock2 { /* u17 - USB */
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <26000000>;
+       };
+};
+
+&can0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can0_default>;
+};
+
+&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c1_default>;
+       pinctrl-1 = <&pinctrl_i2c1_gpio>;
+       scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+       u3: ina260@40 { /* u3 */
+               compatible = "ti,ina260";
+               #io-channel-cells = <1>;
+               label = "ina260-u14";
+               reg = <0x40>;
+       };
+
+       slg7xl45106: gpio@11 { /* u13 - reset logic */
+               compatible = "dlg,slg7xl45106";
+               reg = <0x11>;
+               label = "resetchip";
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names = "USB0_PHY_RESET_B", "",
+                                 "SD_RESET_B", "USB0_HUB_RESET_B",
+                                 "", "PS_GEM0_RESET_B",
+                                 "", "";
+       };
+
+       /* usb5744@2d */
+};
+
+/* USB 3.0 */
+&psgtr {
+       status = "okay";
+       /* usb */
+       clocks = <&clk_26>;
+       clock-names = "ref2";
+};
+
+&usb0 { /* mio52 - mio63 */
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb0_default>;
+       phy-names = "usb3-phy";
+       phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+       reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+       assigned-clock-rates = <250000000>, <20000000>;
+
+       usbhub0: usb-hub { /* u36 */
+               i2c-bus = <&i2c1>;
+               compatible = "microchip,usb5744";
+               reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+       };
+
+       usb2244: usb-sd { /* u41 */
+               compatible = "microchip,usb2244";
+               reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&dwc3_0 {
+       status = "okay";
+       dr_mode = "host";
+       snps,usb3_lpm_capable;
+       maximum-speed = "super-speed";
+};
+
+&gem1 { /* mdio mio50/51 */
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gem1_default>;
+       assigned-clock-rates = <250000000>;
+
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@8 { /* Adin u31 */
+                       reg = <8>;
+                       adi,rx-internal-delay-ps = <2000>;
+                       adi,tx-internal-delay-ps = <2000>;
+                       adi,fifo-depth-bits = <8>;
+                       reset-assert-us = <10>;
+                       reset-deassert-us = <5000>;
+                       reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+/* 2 more ethernet phys u32@2 and u34@3 */
+
+&pinctrl0 { /* required by spec */
+       status = "okay";
+
+       pinctrl_can0_default: can0-default {
+               mux {
+                       function = "can0";
+                       groups = "can0_16_grp";
+               };
+
+               conf {
+                       groups = "can0_16_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO66";
+                       bias-pull-up;
+               };
+
+               conf-tx {
+                       pins = "MIO67";
+                       bias-pull-up;
+                       drive-strength = <4>;
+               };
+       };
+
+       pinctrl_uart0_default: uart0-default {
+               conf {
+                       groups = "uart0_17_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+                       drive-strength = <12>;
+               };
+
+               conf-rx {
+                       pins = "MIO70";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO71";
+                       bias-disable;
+               };
+
+               mux {
+                       groups = "uart0_17_grp";
+                       function = "uart0";
+               };
+       };
+
+       pinctrl_uart1_default: uart1-default {
+               conf {
+                       groups = "uart1_9_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+                       drive-strength = <12>;
+               };
+
+               conf-rx {
+                       pins = "MIO37";
+                       bias-high-impedance;
+               };
+
+               conf-tx {
+                       pins = "MIO36";
+                       bias-disable;
+                       output-enable;
+               };
+
+               mux {
+                       groups = "uart1_9_grp";
+                       function = "uart1";
+               };
+       };
+
+       pinctrl_i2c1_default: i2c1-default {
+               conf {
+                       groups = "i2c1_6_grp";
+                       bias-pull-up;
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux {
+                       groups = "i2c1_6_grp";
+                       function = "i2c1";
+               };
+       };
+
+       pinctrl_i2c1_gpio: i2c1-gpio {
+               conf {
+                       groups = "gpio0_24_grp", "gpio0_25_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               mux {
+                       groups = "gpio0_24_grp", "gpio0_25_grp";
+                       function = "gpio0";
+               };
+       };
+
+       pinctrl_gem1_default: gem1-default {
+               conf {
+                       groups = "ethernet1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO45", "MIO46", "MIO47", "MIO48";
+                       bias-disable;
+                       low-power-disable;
+               };
+
+               conf-bootstrap {
+                       pins = "MIO44", "MIO49";
+                       bias-disable;
+                       output-enable;
+                       low-power-disable;
+               };
+
+               conf-tx {
+                       pins = "MIO38", "MIO39", "MIO40",
+                               "MIO41", "MIO42", "MIO43";
+                       bias-disable;
+                       output-enable;
+                       low-power-enable;
+               };
+
+               conf-mdio {
+                       groups = "mdio1_0_grp";
+                       slew-rate = <SLEW_RATE_SLOW>;
+                       power-source = <IO_STANDARD_LVCMOS18>;
+                       bias-disable;
+                       output-enable;
+               };
+
+               mux-mdio {
+                       function = "mdio1";
+                       groups = "mdio1_0_grp";
+               };
+
+               mux {
+                       function = "ethernet1";
+                       groups = "ethernet1_0_grp";
+               };
+       };
+
+       pinctrl_usb0_default: usb0-default {
+               conf {
+                       groups = "usb0_0_grp";
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO52", "MIO53", "MIO55";
+                       bias-high-impedance;
+                       drive-strength = <12>;
+                       slew-rate = <SLEW_RATE_FAST>;
+               };
+
+               conf-tx {
+                       pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+                       "MIO60", "MIO61", "MIO62", "MIO63";
+                       bias-disable;
+                       output-enable;
+                       drive-strength = <4>;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+
+               mux {
+                       groups = "usb0_0_grp";
+                       function = "usb0";
+               };
+       };
+
+       pinctrl_usb1_default: usb1-default {
+               conf {
+                       groups = "usb1_0_grp";
+                       power-source = <IO_STANDARD_LVCMOS18>;
+               };
+
+               conf-rx {
+                       pins = "MIO64", "MIO65", "MIO67";
+                       bias-high-impedance;
+                       drive-strength = <12>;
+                       slew-rate = <SLEW_RATE_FAST>;
+               };
+
+               conf-tx {
+                       pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+                       "MIO72", "MIO73", "MIO74", "MIO75";
+                       bias-disable;
+                       output-enable;
+                       drive-strength = <4>;
+                       slew-rate = <SLEW_RATE_SLOW>;
+               };
+
+               mux {
+                       groups = "usb1_0_grp";
+                       function = "usb1";
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart0_default>;
+       assigned-clock-rates = <100000000>;
+};
+
+&uart1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1_default>;
+};