imx: ventana: Add new memory configuration

Add memory configuration for an IMX6SDL + 1GB density DRAM.

Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index b839b8900f223d37ddceb765568c63a0abe8c262..e3d4e572c2f196074bb0c44e86fde4c41368ea64 100644 (file)
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -188,6 +188,20 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
        .grp_b7ds = 0x00000030,
 };
 
+/* MT41K64M16JT-125 (1Gb density) */
+static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
+       .mem_speed = 1600,
+       .density = 1,
+       .width = 16,
+       .banks = 8,
+       .rowaddr = 13,
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+};
+
 /* MT41K128M16JT-125 (2Gb density) */
 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
        .mem_speed = 1600,
@@ -219,6 +233,18 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 /*
  * calibration - these are the various CPU/DDR3 combinations we support
  */
+static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x004C004E,
+       .p0_mpwldectrl1 = 0x00440044,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x42440247,
+       .p0_mpdgctrl1 = 0x02310232,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x45424746,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x33382C31,
+};
 
 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
        /* write leveling calibration determine */
@@ -389,7 +415,14 @@ static void spl_dram_init(int width, int size_mb, int board_model)
         *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
         *   mx6_ddr_cfg - chip specific timing/layout details
         */
-       if (width == 16 && size_mb == 256) {
+       if (width == 16 && size_mb == 128) {
+               mem = &mt41k64m16jt_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       ;
+               else
+                       calib = &mx6sdl_64x16_mmdc_calib;
+               debug("1gB density\n");
+       } else if (width == 16 && size_mb == 256) {
                /* 1x 2Gb density chip - same calib as 2x 2Gb */
                mem = &mt41k128m16jt_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
@@ -404,6 +437,14 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                else
                        calib = &mx6sdl_256x16_mmdc_calib;
                debug("4gB density\n");
+       } else if (width == 32 && size_mb == 256) {
+               /* Same calib as width==16, size==128 */
+               mem = &mt41k64m16jt_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       ;
+               else
+                       calib = &mx6sdl_64x16_mmdc_calib;
+               debug("1gB density\n");
        } else if (width == 32 && size_mb == 512) {
                mem = &mt41k128m16jt_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
@@ -411,6 +452,16 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                else
                        calib = &mx6sdl_128x32_mmdc_calib;
                debug("2gB density\n");
+       }  else if (width == 32 && size_mb == 1024) {
+               mem = &mt41k256m16ha_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_256x32_mmdc_calib;
+               else
+                       calib = &mx6sdl_256x32_mmdc_calib;
+               debug("4gB density\n");
+       } else if (width == 64 && size_mb == 512) {
+               mem = &mt41k64m16jt_125;
+               debug("1gB density\n");
        } else if (width == 64 && size_mb == 1024) {
                mem = &mt41k128m16jt_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
@@ -418,13 +469,6 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                else
                        calib = &mx6sdl_128x64_mmdc_calib;
                debug("2gB density\n");
-       } else if (width == 32 && size_mb == 1024) {
-               mem = &mt41k256m16ha_125;
-               if (is_cpu_type(MXC_CPU_MX6Q))
-                       calib = &mx6dq_256x32_mmdc_calib;
-               else
-                       calib = &mx6sdl_256x32_mmdc_calib;
-               debug("4gB density\n");
        } else if (width == 64 && size_mb == 2048) {
                mem = &mt41k256m16ha_125;
                if (is_cpu_type(MXC_CPU_MX6Q))