CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=1024
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_PINCTRL=y
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_DWAPB_GPIO=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_SPEED=100000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_CLK=y
# CONFIG_MMC_WRITE is not set
CONFIG_ARM_PL180_MMCI=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=127
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_CLK=y
CONFIG_ARM_PL180_MMCI=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=127
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
are enabled by default, other may require additional flags or are
enabled by the host driver.
+config SYS_MMC_MAX_BLK_COUNT
+ int "Block count limit"
+ default 65535
+ help
+ The block count limit on MMC based devices. We default to 65535 due
+ to a 16bit register limit on some hardware.
+
config MMC_HW_PARTITIONING
bool "Support for HW partitioning command(eMMC)"
default y
BOOTENV
/* TODO: Remove this once the SD clock is fixed */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024
#endif /* __HIKEY_H */
"loadaddr=20080000\0" \
"ethrotate=yes\0"
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
/** Heap size for U-Boot */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-
/** EMMC specific defines */
#endif /* __OCTEONTX_COMMON_H__ */
*/
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
-/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-/* FIXME */
-/* using smaller max blk cnt to avoid flooding the limited stack we have */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
-#endif
-
/*
* NAND Support
*/
/*
* SDMMC configurations
*/
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-#endif
/*
* Flash configurations
*/
#define PHYS_SDRAM_2 0x8080000000
#define PHYS_SDRAM_2_SIZE 0x180000000
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"load_addr=0xa0000000\0" \
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-
/* Miscellaneous configurable options */
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
/* Minimum partition switch timeout in units of 10-milliseconds */
#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
-/* Set block count limit because of 16 bit register limit on some hardware*/
-#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
-#endif
-
/**
* mmc_get_blk_desc() - Get the block descriptor for an MMC device
*