--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot gpio.h
+ */
+
+#ifndef __ASM_INTEL_PINCTRL_H
+#define __ASM_INTEL_PINCTRL_H
+
+#include <dm/pinctrl.h>
+
+/**
+ * struct pad_config - config for a pad
+ * @pad: offset of pad within community
+ * @pad_config: Pad config data corresponding to DW0, DW1, etc.
+ */
+struct pad_config {
+ int pad;
+ u32 pad_config[4];
+};
+
+#include <asm/arch/gpio.h>
+
+/* GPIO community IOSF sideband clock gating */
+#define MISCCFG_GPSIDEDPCGEN BIT(5)
+/* GPIO community RCOMP clock gating */
+#define MISCCFG_GPRCOMPCDLCGEN BIT(4)
+/* GPIO community RTC clock gating */
+#define MISCCFG_GPRTCDLCGEN BIT(3)
+/* GFX controller clock gating */
+#define MISCCFG_GSXSLCGEN BIT(2)
+/* GPIO community partition clock gating */
+#define MISCCFG_GPDPCGEN BIT(1)
+/* GPIO community local clock gating */
+#define MISCCFG_GPDLCGEN BIT(0)
+/* Enable GPIO community power management configuration */
+#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
+/*
+ * GPIO numbers may not be contiguous and instead will have a different
+ * starting pin number for each pad group.
+ */
+#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
+ group_pad_base) \
+ { \
+ .first_pad = (start_of_group) - (first_of_community), \
+ .size = (end_of_group) - (start_of_group) + 1, \
+ .acpi_pad_base = (group_pad_base), \
+ }
+
+/*
+ * A pad base of -1 indicates that this group uses contiguous numbering
+ * and a pad base should not be used for this group.
+ */
+#define PAD_BASE_NONE -1
+
+/* The common/default group numbering is contiguous */
+#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \
+ INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
+ PAD_BASE_NONE)
+
+/**
+ * struct reset_mapping - logical to actual value for PADRSTCFG in DW0
+ *
+ * Note that the values are expected to be within the field placement of the
+ * register itself. i.e. if the reset field is at 31:30 then the values within
+ * logical and chipset should occupy 31:30.
+ */
+struct reset_mapping {
+ u32 logical;
+ u32 chipset;
+};
+
+/**
+ * struct pad_group - describes the groups within each community
+ *
+ * @first_pad: offset of first pad of the group relative to the community
+ * @size: size of the group
+ * @acpi_pad_base: starting pin number for the pads in this group when they are
+ * used in ACPI. This is only needed if the pins are not contiguous across
+ * groups. Most groups will have this set to PAD_BASE_NONE and use
+ * contiguous numbering for ACPI.
+ */
+struct pad_group {
+ int first_pad;
+ uint size;
+ int acpi_pad_base;
+};
+
+/**
+ * struct pad_community - community of pads
+ *
+ * This describes a community, or each group within a community when multiple
+ * groups exist inside a community
+ *
+ * @name: Community name
+ * @acpi_path: ACPI path
+ * @num_gpi_regs: number of gpi registers in community
+ * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
+ * in each GPI status/en and Host Own Reg
+ * @first_pad: first pad in community
+ * @last_pad: last pad in community
+ * @host_own_reg_0: offset to Host Ownership Reg 0
+ * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0
+ * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0
+ * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0
+ * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0
+ * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg
+ * @gpi_status_offset: specifies offset in struct gpi_status
+ * @port: PCR Port ID
+ * @reset_map: PADRSTCFG logical to chipset mapping
+ * @num_reset_vals: number of values in @reset_map
+ * @groups; list of groups for this community
+ * @num_groups: number of groups
+ */
+struct pad_community {
+ const char *name;
+ const char *acpi_path;
+ size_t num_gpi_regs;
+ size_t max_pads_per_group;
+ uint first_pad;
+ uint last_pad;
+ u16 host_own_reg_0;
+ u16 gpi_int_sts_reg_0;
+ u16 gpi_int_en_reg_0;
+ u16 gpi_smi_sts_reg_0;
+ u16 gpi_smi_en_reg_0;
+ u16 pad_cfg_base;
+ u8 gpi_status_offset;
+ u8 port;
+ const struct reset_mapping *reset_map;
+ size_t num_reset_vals;
+ const struct pad_group *groups;
+ size_t num_groups;
+};
+
+/**
+ * struct intel_pinctrl_priv - private data for each pinctrl device
+ *
+ * @comm: Pad community for this device
+ * @num_cfgs: Number of configuration words for each pad
+ * @itss: ITSS device (for interrupt handling)
+ * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
+ * Each bit represents IRQx Active High Polarity Disable configuration:
+ * when set to 1, the interrupt polarity associated with IRQx is inverted
+ * to appear as Active Low to IOAPIC and vice versa
+ */
+struct intel_pinctrl_priv {
+ const struct pad_community *comm;
+ int num_cfgs;
+ struct udevice *itss;
+ bool itss_pol_cfg;
+};
+
+/* Exported common operations for the pinctrl driver */
+extern const struct pinctrl_ops intel_pinctrl_ops;
+
+/* Exported common probe function for the pinctrl driver */
+int intel_pinctrl_probe(struct udevice *dev);
+
+/**
+ * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
+ *
+ * @dev: Pinctrl device
+ * @comm: Pad community for this device
+ * @num_cfgs: Number of configuration words for each pad
+ * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
+ */
+int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
+ const struct pad_community *comm,
+ int num_cfgs);
+
+/**
+ * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
+ *
+ * The values from PMC register GPE_CFG are passed which is then mapped to
+ * proper groups for MISCCFG. This basically sets the MISCCFG register bits:
+ * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
+ * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
+ * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
+ *
+ * @dev: ITSS device
+ * @gpe0b: Value for GPE0B
+ * @gpe0c: Value for GPE0C
+ * @gpe0d: Value for GPE0D
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d);
+
+/**
+ * pinctrl_config_pads() - Configure a list of pads
+ *
+ * Configures multiple pads using the provided data from the device tree.
+ *
+ * @dev: pinctrl device (any will do)
+ * @pads: Pad data, consisting of a pad number followed by num_cfgs entries
+ * containing the data for that pad (num_cfgs is set by the pinctrl device)
+ * @pads_count: Number of pads to configure
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count);
+
+/**
+ * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use
+ *
+ * This enables the interrupt inputs and clears the status register bits
+ *
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_gpi_clear_int_cfg(void);
+
+/**
+ * pinctrl_config_pads_for_node() - Configure pads
+ *
+ * Set up the pads using the data in a given node
+ *
+ * @dev: pinctrl device (any will do)
+ * @node: Node containing the 'pads' property with the data in it
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node);
+
+/**
+ * pinctrl_read_pads() - Read pad data from a node
+ *
+ * @dev: pinctrl device (any will do, it is just used to get config)
+ * @node: Node to read pad data from
+ * @prop: Property name to use (e.g. "pads")
+ * @padsp: Returns a pointer to an allocated array of pad data, in the format:
+ * <pad>
+ * <pad_config0>
+ * <pad_config1>
+ * ...
+ *
+ * The number of pad config values is set by the pinctrl controller.
+ * The caller must free this array.
+ * @pad_countp: Returns the number of pads read
+ * @ereturn 0 if OK, -ve on error
+ */
+int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
+ u32 **padsp, int *pad_countp);
+
+/**
+ * pinctrl_count_pads() - Count the number of pads in a pad array
+ *
+ * This used used with of-platdata where the array may be smaller than its
+ * maximum size. This function searches for the last pad in the array by finding
+ * the first 'zero' record
+ *
+ * This works out the number of records in the array. Each record has one word
+ * for the pad and num_cfgs words for the config.
+ *
+ * @dev: pinctrl device (any will do)
+ * @pads: Array of pad data
+ * @size: Size of pad data in bytes
+ * @return number of pads represented by the data
+ */
+int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
+
+/**
+ * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers
+ *
+ * @dev: Pinctrl device
+ * @offset: GPIO offset within this device
+ * @return register offset within the GPIO p2sb region
+ */
+u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
+
+/**
+ * intel_pinctrl_get_config_reg() - Get the value of a GPIO register
+ *
+ * @dev: Pinctrl device
+ * @offset: GPIO offset within this device
+ * @return register value within the GPIO p2sb region
+ */
+u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
+
+/**
+ * intel_pinctrl_get_pad() - Get pad information for a pad
+ *
+ * This is used by the GPIO controller to find the pinctrl used by a pad.
+ *
+ * @pad: Pad to check
+ * @devp: Returns pinctrl device containing that pad
+ * @offsetp: Returns offset of pad within that pinctrl device
+ */
+int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
+
+/**
+ * intel_pinctrl_get_acpi_pin() - Get the ACPI pin for a pinctrl pin
+ *
+ * Maps a pinctrl pin (in terms of its offset within the pins controlled by that
+ * pinctrl) to an ACPI GPIO pin-table entry.
+ *
+ * @dev: Pinctrl device to check
+ * @offset: Offset of pin within that device (0 = first)
+ * @return associated ACPI GPIO pin-table entry, or standard pin number if the
+ * ACPI pad base is not set
+ */
+int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset);
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot gpio_defs.h
+ */
+
+#ifndef _ASM_INTEL_PINCTRL_DEFS_H_
+#define _ASM_INTEL_PINCTRL_DEFS_H_
+
+/* This file is included by device trees, so avoid BIT() macros */
+
+#define PAD_CFG0_TX_STATE_BIT 0
+#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
+#define PAD_CFG0_RX_STATE_BIT 1
+#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT)
+#define PAD_CFG0_TX_DISABLE (1 << 8)
+#define PAD_CFG0_RX_DISABLE (1 << 9)
+
+#define PAD_CFG0_MODE_SHIFT 10
+#define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT)
+#define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT)
+
+#define PAD_CFG0_ROUTE_MASK (0xf << 17)
+#define PAD_CFG0_ROUTE_NMI (1 << 17)
+#define PAD_CFG0_ROUTE_SMI (1 << 18)
+#define PAD_CFG0_ROUTE_SCI (1 << 19)
+#define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
+#define PAD_CFG0_RXTENCFG_MASK (3 << 21)
+#define PAD_CFG0_RXINV_MASK (1 << 23)
+#define PAD_CFG0_RX_POL_INVERT (1 << 23)
+#define PAD_CFG0_RX_POL_NONE (0 << 23)
+#define PAD_CFG0_PREGFRXSEL (1 << 24)
+#define PAD_CFG0_TRIG_MASK (3 << 25)
+#define PAD_CFG0_TRIG_LEVEL (0 << 25)
+#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
+#define PAD_CFG0_TRIG_OFF (2 << 25)
+#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
+#define PAD_CFG0_RXRAW1_MASK (1 << 28)
+#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
+#define PAD_CFG0_RESET_MASK (3 << 30)
+#define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
+#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
+#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
+#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
+
+/*
+ * Use the fourth bit in IntSel field to indicate gpio ownership. This field is
+ * RO and hence not used during gpio configuration.
+ */
+#define PAD_CFG1_GPIO_DRIVER (0x1 << 4)
+#define PAD_CFG1_IRQ_MASK (0xff << 0)
+#define PAD_CFG1_IOSTERM_MASK (0x3 << 8)
+#define PAD_CFG1_IOSTERM_SAME (0x0 << 8)
+#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8)
+#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8)
+#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8)
+#define PAD_CFG1_PULL_MASK (0xf << 10)
+#define PAD_CFG1_PULL_NONE (0x0 << 10)
+#define PAD_CFG1_PULL_DN_5K (0x2 << 10)
+#define PAD_CFG1_PULL_DN_20K (0x4 << 10)
+#define PAD_CFG1_PULL_UP_1K (0x9 << 10)
+#define PAD_CFG1_PULL_UP_5K (0xa << 10)
+#define PAD_CFG1_PULL_UP_2K (0xb << 10)
+#define PAD_CFG1_PULL_UP_20K (0xc << 10)
+#define PAD_CFG1_PULL_UP_667 (0xd << 10)
+#define PAD_CFG1_PULL_NATIVE (0xf << 10)
+
+/* Tx enabled driving last value driven, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14)
+/*
+ * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14)
+/*
+ * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14)
+/*
+ * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14)
+/*
+ * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
+ * internally
+ */
+#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14)
+/* Tx enabled driving 0, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14)
+/* Tx enabled driving 1, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14)
+/* Hi-Z, Rx driving 0 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14)
+/* Hi-Z, Rx driving 1 back to its controller internally */
+#define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14)
+/* Tx disabled, Rx enabled */
+#define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14)
+#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */
+/* mask to extract Iostandby bits */
+#define PAD_CFG1_IOSSTATE_MASK (0xf << 14)
+#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
+
+#define PAD_CFG2_DEBEN 1
+/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
+#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1)
+#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1)
+#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1)
+#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1)
+#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1)
+#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1)
+#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1)
+#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1)
+#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1)
+#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1)
+#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1)
+#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1)
+#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1)
+#define PAD_CFG2_DEBOUNCE_MASK 0x1f
+
+/* voltage tolerance 0=3.3V default 1=1.8V tolerant */
+#if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY)
+#define PAD_CFG1_TOL_MASK (0x1 << 25)
+#define PAD_CFG1_TOL_1V8 (0x1 << 25)
+#endif
+
+#define PAD_FUNC(value) PAD_CFG0_MODE_##value
+#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
+#define PAD_PULL(value) PAD_CFG1_PULL_##value
+
+#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
+#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
+
+#define PAD_IRQ_CFG(route, trig, inv) \
+ (PAD_CFG0_ROUTE_##route | \
+ PAD_CFG0_TRIG_##trig | \
+ PAD_CFG0_RX_POL_##inv)
+
+#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
+#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
+ (PAD_CFG0_ROUTE_##route1 | \
+ PAD_CFG0_ROUTE_##route2 | \
+ PAD_CFG0_TRIG_##trig | \
+ PAD_CFG0_RX_POL_##inv)
+#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
+
+#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
+ __pad(__config0) (__config1)
+
+/* Native function configuration */
+#define PAD_CFG_NF(pad, pull, rst, func) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TX_LAST_RXE))
+
+#if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL)
+/*
+ * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not
+ * applicable to all SOCs. Refer EDS.
+ */
+#define PAD_CFG_NF_1V8(pad, pull, rst, func) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\
+ PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8)
+#endif
+
+/* Native function configuration for standby state */
+#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate))
+
+/*
+ * Native function configuration for standby state, also configuring iostandby
+ * as masked
+ */
+#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+ PAD_IOSSTATE(IGNORE))
+
+/*
+ * Native function configuration for standby state, also configuring iosstate
+ * and iosterm
+ */
+#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/* General purpose output, no pullup/down */
+#define PAD_CFG_GPO(pad, val, rst) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+ PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE))
+
+/* General purpose output, with termination specified */
+#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+ PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE))
+
+/* General purpose output, no pullup/down */
+#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+ PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \
+ PAD_CFG1_GPIO_DRIVER)
+
+/* General purpose output */
+#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
+ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
+
+/* General purpose input */
+#define PAD_CFG_GPI(pad, pull, rst) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
+ PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input. The following macro sets the
+ * Host Software Pad Ownership to GPIO Driver mode.
+ */
+#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
+ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_CFG0_RX_DISABLE, \
+ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/* GPIO Interrupt */
+#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \
+ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+/*
+ * No Connect configuration for unused pad.
+ * Both TX and RX are disabled. RX disabling is done to avoid unnecessary
+ * setting of GPI_STS.
+ */
+#define PAD_NC(pad, pull) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
+ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \
+ PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to APIC */
+#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to APIC - with IOStandby Config*/
+#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+/*
+ * The following APIC macros assume the APIC will handle the filtering
+ * on its own end. One just needs to pass an active high message into the
+ * ITSS.
+ */
+#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
+ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
+
+#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
+ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
+
+#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
+ PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
+
+/* General purpose input, routed to SMI */
+#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to SMI */
+#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
+ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
+
+#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
+ PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
+
+/* General purpose input, routed to SCI */
+#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TXD_RXE))
+
+/* General purpose input, routed to SCI */
+#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
+ PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
+
+#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
+ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
+
+#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
+ _PAD_CFG_STRUCT_3(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
+
+#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
+ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
+
+#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
+ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
+
+/* General purpose input, routed to NMI */
+#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
+ PAD_IOSSTATE(TXD_RXE))
+
+#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT)
+/* GPI, GPIO Driver, SCI interrupt */
+#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG(SCI, trig, inv), \
+ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
+ _PAD_CFG_STRUCT(pad, \
+ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
+ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
+ PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE))
+
+#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
+ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
+
+#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */
+
+#endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */
--- /dev/null
+* Intel Apollo Lake pin controller
+
+The Apollo Lake (APL) pin controller is used to select the function of a pin
+and to configure it.
+
+Required properties:
+- compatible: "intel,apl-pinctrl"
+- intel,p2sb-port-id: Port ID number within the parent P2SB
+- reg: PCI address of the controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+Optional subnodes:
+
+GPIO nodes may be added as children of the pinctrl nodes. See intel,apl-gpio
+for the binding.
+
+
+Example:
+
+...
+{
+ p2sb: p2sb@d,0 {
+ reg = <0x02006810 0 0 0 0>;
+ compatible = "intel,apl-p2sb";
+ early-regs = <IOMAP_P2SB_BAR 0x100000>;
+
+ n {
+ compatible = "intel,apl-pinctrl";
+ intel,p2sb-port-id = <PID_GPIO_N>;
+ gpio_n: gpio-n {
+ compatible = "intel,apl-gpio";
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+...
This option is to enable the AT91 pinctrl driver for AT91 PIO4
controller which is available on SAMA5D2 SoC.
+config PINCTRL_INTEL
+ bool "Standard Intel pin-control and pin-mux driver"
+ help
+ Recent Intel chips such as Apollo Lake (APL) use a common pin control
+ and GPIO scheme. The settings for this come from an SoC-specific
+ driver which must be separately enabled. The driver supports setting
+ pins on start-up and changing the GPIO attributes.
+
config PINCTRL_PIC32
bool "Microchip PIC32 pin-control and pin-mux driver"
depends on DM && MACH_PIC32
source "drivers/pinctrl/broadcom/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/mscc/Kconfig"
obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
+obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
--- /dev/null
+#
+# Intel PINCTRL drivers
+#
+
+if PINCTRL_INTEL
+
+config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
+ def_bool y
+
+config INTEL_PINCTRL_PADCFG_PADTOL
+ def_bool n
+
+config INTEL_PINCTRL_IOSTANDBY
+ def_bool y
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += pinctrl.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Taken partly from coreboot gpio.c
+ *
+ * Pinctrl is modelled as a separate device-tree node and device for each
+ * 'community' (basically a set of GPIOs). The separate devices work together
+ * and many functions permit any PINCTRL device to be provided as a parameter,
+ * since the pad numbering is unique across all devices.
+ *
+ * Each pinctrl has a single child GPIO device to handle GPIO access and
+ * therefore there is a simple GPIO driver included in this file.
+ */
+
+#define LOG_CATEGORY UCLASS_GPIO
+
+#include <common.h>
+#include <dm.h>
+#include <irq.h>
+#include <p2sb.h>
+#include <spl.h>
+#include <asm-generic/gpio.h>
+#include <asm/intel_pinctrl.h>
+#include <asm/intel_pinctrl_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/itss.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define GPIO_DW_SIZE(x) (sizeof(u32) * (x))
+#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num))
+#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0)
+#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1)
+
+#define MISCCFG_GPE0_DW0_SHIFT 8
+#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
+#define MISCCFG_GPE0_DW1_SHIFT 12
+#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
+#define MISCCFG_GPE0_DW2_SHIFT 16
+#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+
+#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \
+ ((group) * sizeof(u32)))
+#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
+ ((group) * sizeof(u32)))
+#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
+ ((group) * sizeof(uint32_t)))
+#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
+ ((group) * sizeof(uint32_t)))
+
+/**
+ * relative_pad_in_comm() - Get the relative position of a GPIO
+ *
+ * This finds the position of a GPIO within a community
+ *
+ * @comm: Community to search
+ * @gpio: Pad number to look up (assumed to be valid)
+ * @return offset, 0 for first GPIO in community
+ */
+static size_t relative_pad_in_comm(const struct pad_community *comm,
+ uint gpio)
+{
+ return gpio - comm->first_pad;
+}
+
+/**
+ * pinctrl_group_index() - Find group for a a pad
+ *
+ * Find the group within the community that the pad is a part of
+ *
+ * @comm: Community to search
+ * @relative_pad: Pad to look up
+ * @return group number if found (see community_n_groups, etc.), or
+ * -ESPIPE if no groups, or -ENOENT if not found
+ */
+static int pinctrl_group_index(const struct pad_community *comm,
+ uint relative_pad)
+{
+ int i;
+
+ if (!comm->groups)
+ return -ESPIPE;
+
+ /* find the base pad number for this pad's group */
+ for (i = 0; i < comm->num_groups; i++) {
+ if (relative_pad >= comm->groups[i].first_pad &&
+ relative_pad < comm->groups[i].first_pad +
+ comm->groups[i].size)
+ return i;
+ }
+
+ return -ENOENT;
+}
+
+static int pinctrl_group_index_scaled(const struct pad_community *comm,
+ uint relative_pad, size_t scale)
+{
+ int ret;
+
+ ret = pinctrl_group_index(comm, relative_pad);
+ if (ret < 0)
+ return ret;
+
+ return ret * scale;
+}
+
+static int pinctrl_within_group(const struct pad_community *comm,
+ uint relative_pad)
+{
+ int ret;
+
+ ret = pinctrl_group_index(comm, relative_pad);
+ if (ret < 0)
+ return ret;
+
+ return relative_pad - comm->groups[ret].first_pad;
+}
+
+static u32 pinctrl_bitmask_within_group(const struct pad_community *comm,
+ uint relative_pad)
+{
+ return 1U << pinctrl_within_group(comm, relative_pad);
+}
+
+/**
+ * pinctrl_get_device() - Find the device for a particular pad
+ *
+ * Each pinctr, device is attached to one community and this supports a number
+ * of pads. This function finds the device which controls a particular pad.
+ *
+ * @pad: Pad to check
+ * @devp: Returns the device for that pad
+ * @return 0 if OK, -ENOTBLK if no device was found for the given pin
+ */
+static int pinctrl_get_device(uint pad, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ /*
+ * We have to probe each one of these since the community link is only
+ * attached in intel_pinctrl_ofdata_to_platdata().
+ */
+ uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) {
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pad_community *comm = priv->comm;
+
+ if (pad >= comm->first_pad && pad <= comm->last_pad) {
+ *devp = dev;
+ return 0;
+ }
+ }
+ printf("pad %d not found\n", pad);
+
+ return -ENOTBLK;
+}
+
+int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp)
+{
+ const struct pad_community *comm;
+ struct intel_pinctrl_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = pinctrl_get_device(pad, &dev);
+ if (ret)
+ return log_msg_ret("pad", ret);
+ priv = dev_get_priv(dev);
+ comm = priv->comm;
+ *devp = dev;
+ *offsetp = relative_pad_in_comm(comm, pad);
+
+ return 0;
+}
+
+static int pinctrl_configure_owner(struct udevice *dev,
+ const struct pad_config *cfg,
+ const struct pad_community *comm)
+{
+ u32 hostsw_own;
+ u16 hostsw_own_offset;
+ int pin;
+ int ret;
+
+ pin = relative_pad_in_comm(comm, cfg->pad);
+
+ /*
+ * Based on the gpio pin number configure the corresponding bit in
+ * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
+ */
+ hostsw_own_offset = comm->host_own_reg_0;
+ ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32));
+ if (ret < 0)
+ return ret;
+ hostsw_own_offset += ret;
+
+ hostsw_own = pcr_read32(dev, hostsw_own_offset);
+
+ /*
+ *The 4th bit in pad_config 1 (RO) is used to indicate if the pad
+ * needs GPIO driver ownership. Set the bit if GPIO driver ownership
+ * requested, otherwise clear the bit.
+ */
+ if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)
+ hostsw_own |= pinctrl_bitmask_within_group(comm, pin);
+ else
+ hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin);
+
+ pcr_write32(dev, hostsw_own_offset, hostsw_own);
+
+ return 0;
+}
+
+static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg,
+ const struct pad_community *comm)
+{
+ u32 value;
+ u16 sts_reg;
+ u16 en_reg;
+ int group;
+ int pin;
+ int ret;
+
+ if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI)
+ return 0;
+
+ pin = relative_pad_in_comm(comm, cfg->pad);
+ ret = pinctrl_group_index(comm, pin);
+ if (ret < 0)
+ return ret;
+ group = ret;
+
+ sts_reg = GPI_SMI_STS_OFFSET(comm, group);
+ value = pcr_read32(dev, sts_reg);
+ /* Write back 1 to reset the sts bits */
+ pcr_write32(dev, sts_reg, value);
+
+ /* Set enable bits */
+ en_reg = GPI_SMI_EN_OFFSET(comm, group);
+ pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin));
+
+ return 0;
+}
+
+static int pinctrl_configure_itss(struct udevice *dev,
+ const struct pad_config *cfg,
+ uint pad_cfg_offset)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (!priv->itss_pol_cfg)
+ return -ENOSYS;
+
+ int irq;
+
+ /*
+ * Set up ITSS polarity if pad is routed to APIC.
+ *
+ * The ITSS takes only active high interrupt signals. Therefore,
+ * if the pad configuration indicates an inversion assume the
+ * intent is for the ITSS polarity. Before forwarding on the
+ * request to the APIC there's an inversion setting for how the
+ * signal is forwarded to the APIC. Honor the inversion setting
+ * in the GPIO pad configuration so that a hardware active low
+ * signal looks that way to the APIC (double inversion).
+ */
+ if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC))
+ return 0;
+
+ irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset));
+ irq &= PAD_CFG1_IRQ_MASK;
+ if (!irq) {
+ log_err("GPIO %u doesn't support APIC routing\n", cfg->pad);
+
+ return -EPROTONOSUPPORT;
+ }
+ irq_set_polarity(priv->itss, irq,
+ cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT);
+
+ return 0;
+}
+
+/* Number of DWx config registers can be different for different SOCs */
+static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad)
+{
+ const struct pad_community *comm = priv->comm;
+ size_t offset;
+
+ offset = relative_pad_in_comm(comm, pad);
+ offset *= GPIO_DW_SIZE(priv->num_cfgs);
+
+ return offset + comm->pad_cfg_base;
+}
+
+static int pinctrl_pad_reset_config_override(const struct pad_community *comm,
+ u32 config_value)
+{
+ const struct reset_mapping *rst_map = comm->reset_map;
+ int i;
+
+ /* Logical reset values equal chipset values */
+ if (!rst_map || !comm->num_reset_vals)
+ return config_value;
+
+ for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
+ if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
+ config_value &= ~PAD_CFG0_RESET_MASK;
+ config_value |= rst_map->chipset;
+
+ return config_value;
+ }
+ }
+ log_err("Logical-to-Chipset mapping not found\n");
+
+ return -ENOENT;
+}
+
+static const int mask[4] = {
+ PAD_CFG0_TX_STATE |
+ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |
+ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK |
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL |
+ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK |
+ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK,
+
+#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY
+ PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK,
+#else
+ PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK,
+#endif
+
+ PAD_CFG2_DEBOUNCE_MASK,
+
+ 0,
+};
+
+/**
+ * pinctrl_configure_pad() - Configure a pad
+ *
+ * @dev: Pinctrl device containing the pad (see pinctrl_get_device())
+ * @cfg: Configuration to apply
+ * @return 0 if OK, -ve on error
+ */
+static int pinctrl_configure_pad(struct udevice *dev,
+ const struct pad_config *cfg)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pad_community *comm = priv->comm;
+ uint config_offset;
+ u32 pad_conf, soc_pad_conf;
+ int ret;
+ int i;
+
+ if (IS_ERR(comm))
+ return PTR_ERR(comm);
+ config_offset = pad_config_offset(priv, cfg->pad);
+ for (i = 0; i < priv->num_cfgs; i++) {
+ pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i));
+
+ soc_pad_conf = cfg->pad_config[i];
+ if (i == 0) {
+ ret = pinctrl_pad_reset_config_override(comm,
+ soc_pad_conf);
+ if (ret < 0)
+ return ret;
+ soc_pad_conf = ret;
+ }
+ soc_pad_conf &= mask[i];
+ soc_pad_conf |= pad_conf & ~mask[i];
+
+ log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n",
+ comm->port, relative_pad_in_comm(comm, cfg->pad), i,
+ pad_conf,/* old value */
+ /* value passed from pinctrl table */
+ cfg->pad_config[i],
+ soc_pad_conf); /*new value*/
+ pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i),
+ soc_pad_conf);
+ }
+ ret = pinctrl_configure_itss(dev, cfg, config_offset);
+ if (ret && ret != -ENOSYS)
+ return log_msg_ret("itss config failed", ret);
+ ret = pinctrl_configure_owner(dev, cfg, comm);
+ if (ret)
+ return ret;
+ ret = gpi_enable_smi(dev, cfg, comm);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pad_community *comm = priv->comm;
+ uint config_offset;
+
+ assert(device_get_uclass_id(dev) == UCLASS_PINCTRL);
+ config_offset = comm->pad_cfg_base + offset *
+ GPIO_DW_SIZE(priv->num_cfgs);
+
+ return config_offset;
+}
+
+u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
+{
+ uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset);
+
+ return pcr_read32(dev, config_offset);
+}
+
+int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pad_community *comm = priv->comm;
+ int group;
+
+ group = pinctrl_group_index(comm, offset);
+
+ /* If pad base is not set then use GPIO number as ACPI pin number */
+ if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE)
+ return comm->first_pad + offset;
+
+ /*
+ * If this group has a non-zero pad base then compute the ACPI pin
+ * number from the pad base and the relative pad in the group.
+ */
+ return comm->groups[group].acpi_pad_base +
+ pinctrl_within_group(comm, offset);
+}
+
+int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d)
+{
+ struct udevice *pinctrl_dev;
+ u32 misccfg_value;
+ u32 misccfg_clr;
+ int ret;
+
+ /*
+ * Get the group here for community specific MISCCFG register.
+ * If any of these returns -1 then there is some error in devicetree
+ * where the group is probably hardcoded and does not comply with the
+ * PMC group defines. So we return from here and MISCFG is set to
+ * default.
+ */
+ ret = irq_route_pmc_gpio_gpe(itss, gpe0b);
+ if (ret)
+ return ret;
+ gpe0b = ret;
+
+ ret = irq_route_pmc_gpio_gpe(itss, gpe0c);
+ if (ret)
+ return ret;
+ gpe0c = ret;
+
+ ret = irq_route_pmc_gpio_gpe(itss, gpe0d);
+ if (ret)
+ return ret;
+ gpe0d = ret;
+
+ misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT;
+ misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT;
+ misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT;
+
+ /* Program GPIO_MISCCFG */
+ misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK |
+ MISCCFG_GPE0_DW0_MASK;
+
+ log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr,
+ misccfg_value);
+ uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) {
+ pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr,
+ misccfg_value);
+ }
+
+ return 0;
+}
+
+int pinctrl_gpi_clear_int_cfg(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_PINCTRL, &uc);
+ if (ret)
+ return log_msg_ret("pinctrl uc", ret);
+ uclass_foreach_dev(dev, uc) {
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pad_community *comm = priv->comm;
+ uint sts_value;
+ int group;
+
+ for (group = 0; group < comm->num_gpi_regs; group++) {
+ /* Clear the enable register */
+ pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0);
+
+ /* Read and clear the set status register bits*/
+ sts_value = pcr_read32(dev,
+ GPI_IS_OFFSET(comm, group));
+ pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value);
+ }
+ }
+
+ return 0;
+}
+
+int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ const u32 *ptr;
+ int i;
+
+ log_debug("%s: pads_count=%d\n", __func__, pads_count);
+ for (ptr = pads, i = 0; i < pads_count;
+ ptr += 1 + priv->num_cfgs, i++) {
+ struct udevice *pad_dev = NULL;
+ struct pad_config *cfg;
+ int ret;
+
+ cfg = (struct pad_config *)ptr;
+ ret = pinctrl_get_device(cfg->pad, &pad_dev);
+ if (ret)
+ return ret;
+ ret = pinctrl_configure_pad(pad_dev, cfg);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
+ u32 **padsp, int *pad_countp)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 *pads;
+ int size;
+ int ret;
+
+ *padsp = NULL;
+ *pad_countp = 0;
+ size = ofnode_read_size(node, prop);
+ if (size < 0)
+ return 0;
+
+ pads = malloc(size);
+ if (!pads)
+ return -ENOMEM;
+ size /= sizeof(fdt32_t);
+ ret = ofnode_read_u32_array(node, prop, pads, size);
+ if (ret) {
+ free(pads);
+ return ret;
+ }
+ *pad_countp = size / (1 + priv->num_cfgs);
+ *padsp = pads;
+
+ return 0;
+}
+
+int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ int count = 0;
+ int i;
+
+ for (i = 0; i < size;) {
+ u32 val;
+ int j;
+
+ for (val = j = 0; j < priv->num_cfgs + 1; j++)
+ val |= pads[i + j];
+ if (!val)
+ break;
+ count++;
+ i += priv->num_cfgs + 1;
+ }
+
+ return count;
+}
+
+int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node)
+{
+ int pads_count;
+ u32 *pads;
+ int ret;
+
+ if (device_get_uclass_id(dev) != UCLASS_PINCTRL)
+ return log_msg_ret("uclass", -EPROTONOSUPPORT);
+ ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count);
+ if (ret)
+ return log_msg_ret("no pads", ret);
+ ret = pinctrl_config_pads(dev, pads, pads_count);
+ free(pads);
+ if (ret)
+ return log_msg_ret("pad config", ret);
+
+ return 0;
+}
+
+int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
+ const struct pad_community *comm,
+ int num_cfgs)
+{
+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!comm) {
+ log_err("Cannot find community for pid %d\n", pplat->pid);
+ return -EDOM;
+ }
+ ret = uclass_first_device_err(UCLASS_IRQ, &priv->itss);
+ if (ret)
+ return log_msg_ret("Cannot find ITSS", ret);
+ priv->comm = comm;
+ priv->num_cfgs = num_cfgs;
+
+ return 0;
+}
+
+int intel_pinctrl_probe(struct udevice *dev)
+{
+ struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->itss_pol_cfg = true;
+
+ return 0;
+}
+
+const struct pinctrl_ops intel_pinctrl_ops = {
+ /* No operations are supported, but DM expects this to be present */
+};
projects / u-boot.git / commitdiff
