arm: mach-k3: j784s4: Add clk and power support for wkup_uart

Add clk and device data which can be used by wkup_uart driver
to configure clocks and PSC.

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>

diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 793bcac93245f5b8fcdd80e8257f549faeae6523..97d969271ecdf571d493366d1130ba52dc78adc2 100644 (file)
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -67,6 +67,16 @@ static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
        "gluelogic_hfosc0_clkout",
 };
 
+static const char * const wkup_usart_clksel_out0_parents[] = {
+       "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+       "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_usart_mcupll_bypass_out0_parents[] = {
+       "wkup_usart_clksel_out0",
+       "gluelogic_hfosc0_clkout",
+};
+
 static const char * const main_pll_hfosc_sel_out0_parents[] = {
        "gluelogic_hfosc0_clkout",
        "board_0_hfosc1_clk_out",
@@ -206,7 +216,7 @@ static const struct clk_data clk_list[] = {
        CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
        CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
        CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
-       CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
+       CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0, 96000000),
        CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
        CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
        CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
@@ -216,6 +226,8 @@ static const struct clk_data clk_list[] = {
        CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
        CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
        CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
+       CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
+       CLK_MUX("wkup_usart_mcupll_bypass_out0", wkup_usart_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
        CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
        CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
        CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
@@ -409,6 +421,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
        DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
        DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+       DEV_CLK(397, 0, "wkup_usart_mcupll_bypass_out0"),
+       DEV_CLK(397, 1, "wkup_usart_clksel_out0"),
+       DEV_CLK(397, 2, "gluelogic_hfosc0_clkout"),
+       DEV_CLK(397, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
        DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),

diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index d66ba8b16e091f7afc567357203662b024567e84..b32b4ba9588001b06176143af92c2d7b1903adfd 100644 (file)
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -62,6 +62,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(149, &soc_lpsc_list[0]),
        PSC_DEV(167, &soc_lpsc_list[1]),
        PSC_DEV(279, &soc_lpsc_list[1]),
+       PSC_DEV(397, &soc_lpsc_list[1]),
        PSC_DEV(161, &soc_lpsc_list[2]),
        PSC_DEV(162, &soc_lpsc_list[3]),
        PSC_DEV(160, &soc_lpsc_list[4]),