ddr: socfpga: Fix IO in Arria10 DDR driver

The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 29ea7492f30299acc8a282ecfd044d068b052c56..6724eb29f1e9831405a2309e1cca395d351adadd 100644 (file)
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -304,7 +304,7 @@ static void sdram_mmr_init(void)
         *      bit[9:6] = Minor Release #
         *      bit[14:10] = Major Release #
         */
-       if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+       if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
                update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
                writel(((update_value & 0xFF) >> 5),
                       &socfpga_ecc_hmc_base->ddrioctrl);
@@ -394,7 +394,7 @@ static void sdram_mmr_init(void)
                        caltim0_cfg_act_to_rdwr -
                        (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 
-       io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+       io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
                      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
                      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
                      /* Up to here was in memory cycles so divide by 2 */
@@ -424,7 +424,7 @@ static void sdram_mmr_init(void)
                &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 
        /* Configure the read latency [0xFFD12414] */
-       writel(((socfpga_io48_mmr_base->dramtiming0 &
+       writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
                ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
                DDR_READ_LATENCY_DELAY,
                &socfpga_noc_ddr_scheduler_base->