mmc: tmio: Do not set divider to 1 in DDR mode

The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 3ba2f074603c04d1d47bb95b170cb6eb7acc69a6..424b60ce520596e41d3e86c6ed005d095ac2d01f 100644 (file)
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -574,6 +574,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
 
        divisor = DIV_ROUND_UP(mclk, mmc->clock);
 
+       /* Do not set divider to 0xff in DDR mode */
+       if (mmc->ddr_mode && (divisor == 1))
+               divisor = 2;
+
        if (divisor <= 1)
                val = (priv->caps & TMIO_SD_CAP_RCAR) ?
                      TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;