arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs

Add mcu cpsw nuss pinmux and phy defs required by cpsw.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 18b611990fc71711be4e0db7c6c1f90cb5ded115..844a5cd96ad4c1655c07c08a736caea8196cad49 100644 (file)
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/pinctrl/k3.h>
 #include <dt-bindings/dma/k3-udma.h>
+#include <dt-bindings/net/ti-dp83867.h>
 
 / {
        chosen {
@@ -300,6 +301,32 @@
        u-boot,dm-spl;
 };
 
+&wkup_pmx0 {
+       mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+               pinctrl-single,pins = <
+                       AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
+                       AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
+                       AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
+                       AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
+                       AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
+                       AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
+                       AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
+                       AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
+                       AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
+                       AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
+                       AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+                       AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
+               >;
+       };
+
+       mcu_mdio_pins_default: mcu_mdio1_pins_default {
+               pinctrl-single,pins = <
+                       AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+                       AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+               >;
+       };
+};
+
 &main_uart0 {
        u-boot,dm-spl;
        pinctrl-names = "default";
@@ -323,3 +350,35 @@
        pinctrl-0 = <&main_mmc1_pins_default>;
        sdhci-caps-mask = <0x7 0x0>;
 };
+
+&mcu_cpsw {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+};
+
+&cpsw_port1 {
+       phy-mode = "rgmii-id";
+       phy-handle = <&phy0>;
+};
+
+&mcu_cpsw {
+       reg = <0x0 0x46000000 0x0 0x200000>,
+             <0x0 0x40f00200 0x0 0x2>;
+       reg-names = "cpsw_nuss", "mac_efuse";
+
+       cpsw-phy-sel@40f04040 {
+               compatible = "ti,am654-cpsw-phy-sel";
+               reg= <0x0 0x40f04040 0x0 0x4>;
+               reg-names = "gmii-sel";
+       };
+};