FSL PCI: Configure PCIe reference ratio

Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.

This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 375b8549c595a256e9088cb7ddbb423c5d3c5cb2..b4c855668613938267f4f20ec8ac2786ec423aaa 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -321,6 +321,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
        pci_setup_indirect(hose, cfg_addr, cfg_data);
 
+#ifdef PEX_CCB_DIV
+       /* Configure the PCIE controller core clock ratio */
+       pci_hose_write_config_dword(hose, dev, 0x440,
+                                   ((gd->bus_clk / 1000000) *
+                                    (16 / PEX_CCB_DIV)) / 333);
+#endif
        block_rev = in_be32(&pci->block_rev1);
        if (PEX_IP_BLK_REV_2_2 <= block_rev) {
                pi = &pci->pit[2];      /* 0xDC0 */