struct tmio_sd_plat *plat = dev_get_plat(dev);
/* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ if (((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() <= 2)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
+ (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
+ ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
+ (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ if (((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() >= 2)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() == 2)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
+ (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ if ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() > 2)) {
priv->adjust_hs400_enable = true;
}
/* M3W+ bad taps */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ if ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 3))
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
/* M3N can use HS400 with manual adjustment */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
+ if (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
}
/* E3 can use HS400 with manual adjustment */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
+ if (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
}
/* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ if (((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 2)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() <= 3)))
priv->nrtaps = 4;
priv->nrtaps = 8;
#endif
/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ if (((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ ((renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
(rmobile_get_cpu_rev_fraction() == 0)))
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
/* V3M handles SD0H differently than other Gen3 SoCs */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
+ if (renesas_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
priv->needs_clkh_fallback = true;
else
priv->needs_clkh_fallback = false;