#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */
#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */
+#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
bool
select IMXRT
+config IMXRT1170
+ bool
+ select IMXRT
+
config SYS_SOC
default "imxrt"
bool "Support imxrt1050 EVK board"
select IMXRT1050
+config TARGET_IMXRT1170_EVK
+ bool "Support imxrt1170 EVK board"
+ select IMXRT1170
+
endchoice
source "board/freescale/imxrt1020-evk/Kconfig"
source "board/freescale/imxrt1050-evk/Kconfig"
+source "board/freescale/imxrt1170-evk/Kconfig"
endif
return MXC_CPU_IMXRT1020 << 12;
#elif defined(CONFIG_IMXRT1050)
return MXC_CPU_IMXRT1050 << 12;
+#elif defined(CONFIG_IMXRT1170)
+ return MXC_CPU_IMXRT1170 << 12;
#else
#error This IMXRT SoC is not supported
#endif
--- /dev/null
+if TARGET_IMXRT1170_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1170-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt1170"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1170-evk"
+
+config IMX_CONFIG
+ default "board/freescale/imxrt1170-evk/imximage.cfg"
+
+endif
--- /dev/null
+IMXRT1170 EVALUATION KIT
+M: Giulio Benetti <giulio.benetti@benettiengineering.com>
+M: Jesse Taube <Mr.Bossman075@gmail.com>
+S: Maintained
+F: board/freescale/imxrt1170-evk
+F: include/configs/imxrt1170-evk.h
+F: configs/imxrt1170-evk_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y := imxrt1170-evk.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
+ * Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ preloader_console_init();
+ spl_dram_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}