struct sun4i_spi_plat {
struct sun4i_spi_variant *variant;
u32 base;
- u32 max_hz;
};
struct sun4i_spi_priv {
unsigned int div;
u32 reg;
+ /*
+ * The uclass should take care that this won't happen. But anyway,
+ * avoid a div-by-zero exception.
+ */
+ if (!priv->freq)
+ return;
+
/*
* Setup clock divider.
*
static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
{
- struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
- if (speed > plat->max_hz)
- speed = plat->max_hz;
+ if (speed > SUN4I_SPI_MAX_RATE)
+ speed = SUN4I_SPI_MAX_RATE;
if (speed < SUN4I_SPI_MIN_RATE)
speed = SUN4I_SPI_MIN_RATE;
priv->variant = plat->variant;
priv->base = plat->base;
- priv->freq = plat->max_hz;
return 0;
}
static int sun4i_spi_of_to_plat(struct udevice *bus)
{
struct sun4i_spi_plat *plat = dev_get_plat(bus);
- int node = dev_of_offset(bus);
plat->base = dev_read_addr(bus);
plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
- plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency",
- SUN4I_SPI_DEFAULT_RATE);
-
- if (plat->max_hz > SUN4I_SPI_MAX_RATE)
- plat->max_hz = SUN4I_SPI_MAX_RATE;
return 0;
}