ARM: dts: imx6qdl-icore: Add FEC support

Add FEC dts support for Engicam i.CoreM6 dql modules.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index f424cd5a1afffa38ebe5b32458435978295ea26f..a485c3eb95c6d4e392a786dd92e0a391b06a028b 100644 (file)
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -75,6 +75,14 @@
        assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 };
 
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet>;
+       phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+       phy-mode = "rmii";
+       status = "okay";
+};
+
 &gpmi {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -118,6 +126,22 @@
 };
 
 &iomuxc {
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
+                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
+                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                       MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
+                       MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
+                       MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
+                       MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                       MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
+                       MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+               >;
+       };
+
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020