ARM: tegra: Disable SPL and non-cached memory on 64-bit

For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 7b4c0d70636e624160492839174a2065172ef3a9..49fa8b321064e533c0512820c44d8e0b4bb4ebbf 100644 (file)
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -43,7 +43,9 @@
 #define CONFIG_SYS_MALLOC_LEN          (4 << 20)       /* 4MB  */
 #endif
 
+#ifndef CONFIG_ARM64
 #define CONFIG_SYS_NONCACHED_MEMORY    (1 << 20)       /* 1 MiB */
+#endif
 
 /*
  * NS16550 Configuration
@@ -101,9 +103,11 @@
 #define CONFIG_SYS_MEMTEST_START       (NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 0x100000)
 
+#ifndef CONFIG_ARM64
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_USE_ARCH_MEMCPY
 #endif
+#endif
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map