clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 5f6a5fbe4cbaeb03c13aff46a88e9b2c0884c960..6a6fe4775ddd7571b891585566fab1b1599778e2 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -95,6 +95,13 @@ enum {
        CLK_SARADC_DIV_CON_WIDTH        = 8,
 
        /* CLKSEL43_CON */
+       GMAC_DIV_CON_SHIFT              = 0x0,
+       GMAC_DIV_CON_MASK               = GENMASK(4, 0),
+       GMAC_PLL_SHIFT                  = 6,
+       GMAC_PLL_MASK                   = GENMASK(7, 6),
+       GMAC_PLL_SELECT_NEW             = (0x0 << GMAC_PLL_SHIFT),
+       GMAC_PLL_SELECT_CODEC           = (0x1 << GMAC_PLL_SHIFT),
+       GMAC_PLL_SELECT_GENERAL         = (0x2 << GMAC_PLL_SHIFT),
        GMAC_MUX_SEL_EXTCLK             = BIT(8),
 
        /* CLKSEL51_CON */

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index a8319917bb5585a4ac605df6d01940706684ad20..3364e6ac93f5b85d0972a4af5d53312387b8225c 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -311,15 +311,43 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
 #endif
 
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
-                                ulong clk_id, ulong set_rate)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
 {
+       ulong ret;
+
        /*
-        * This models the 'assigned-clock-parents = <&ext_gmac>' from
-        * the DTS and switches to the 'ext_gmac' clock parent.
+        * The gmac clock can be derived either from an external clock
+        * or can be generated from internally by a divider from SCLK_MAC.
         */
-       rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
-       return set_rate;
+       if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
+               /* An external clock will always generate the right rate... */
+               ret = set_rate;
+       } else {
+               u32 con = readl(&cru->clksel_con[43]);
+               ulong pll_rate;
+               u8 div;
+
+               if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+                   GMAC_PLL_SELECT_GENERAL)
+                       pll_rate = GPLL_HZ;
+               else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+                        GMAC_PLL_SELECT_CODEC)
+                       pll_rate = CPLL_HZ;
+               else
+                       /* CPLL is not set */
+                       return -EPERM;
+
+               div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
+               if (div <= 0x1f)
+                       rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
+                                    div << GMAC_DIV_CON_SHIFT);
+               else
+                       debug("Unsupported div for gmac:%d\n", div);
+
+               return DIV_TO_RATE(pll_rate, div);
+       }
+
+       return ret;
 }
 #endif
 
@@ -479,7 +507,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
        case SCLK_MAC:
                /* select the external clock */
-               ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
+               ret = rk3368_gmac_set_clk(priv->cru, rate);
                break;
 #endif
        case SCLK_SARADC:
@@ -492,9 +520,58 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
        return ret;
 }
 
+static int rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+       struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+       struct rk3368_cru *cru = priv->cru;
+       const char *clock_output_name;
+       int ret;
+
+       /*
+        * If the requested parent is in the same clock-controller and
+        * the id is SCLK_MAC ("sclk_mac"), switch to the internal
+        * clock.
+        */
+       if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
+               debug("%s: switching GAMC to SCLK_MAC\n", __func__);
+               rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+               return 0;
+       }
+
+       /*
+        * Otherwise, we need to check the clock-output-names of the
+        * requested parent to see if the requested id is "ext_gmac".
+        */
+       ret = dev_read_string_index(parent->dev, "clock-output-names",
+                                   parent->id, &clock_output_name);
+       if (ret < 0)
+               return -ENODATA;
+
+       /* If this is "ext_gmac", switch to the external clock input */
+       if (!strcmp(clock_output_name, "ext_gmac")) {
+               debug("%s: switching GMAC to external clock\n", __func__);
+               rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+               return 0;
+       }
+
+       return -EINVAL;
+}
+
+static int rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       switch (clk->id) {
+       case SCLK_MAC:
+               return rk3368_gmac_set_parent(clk, parent);
+       }
+
+       debug("%s: unsupported clk %ld\n", __func__, clk->id);
+       return -ENOENT;
+}
+
 static struct clk_ops rk3368_clk_ops = {
        .get_rate = rk3368_clk_get_rate,
        .set_rate = rk3368_clk_set_rate,
+       .set_parent = rk3368_clk_set_parent,
 };
 
 static int rk3368_clk_probe(struct udevice *dev)