clk: at91: clk-generated: fix incorrect index of clk source

Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 461b5b2c9ad3da263fe9b544f3b475a3a582a069..2aacbaef0c091a442fc876cc90e439b6b879700c 100644 (file)
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -53,16 +53,17 @@ static ulong generic_clk_get_rate(struct clk *clk)
        struct clk parent;
        ulong clk_rate;
        u32 tmp, gckdiv;
-       u8 parent_id;
+       u8 clock_source, parent_index;
        int ret;
 
        writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
        tmp = readl(&pmc->pcr);
-       parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
+       clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
                    AT91_PMC_PCR_GCKCSS_MASK;
        gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
 
-       ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent);
+       parent_index = clock_source - 1;
+       ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
        if (ret)
                return 0;
 
@@ -82,7 +83,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
        ulong tmp_rate, best_rate = rate, parent_rate;
        int tmp_diff, best_diff = -1;
        u32 div, best_div = 0;
-       u8 best_parent_id = 0;
+       u8 best_parent_index, best_clock_source = 0;
        u8 i;
        u32 tmp;
        int ret;
@@ -106,7 +107,8 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
 
                                best_div = div - 1;
                                best_parent = parent;
-                               best_parent_id = i;
+                               best_parent_index = i;
+                               best_clock_source = best_parent_index + 1;
                        }
 
                        if (!best_diff || tmp_rate < rate)
@@ -127,7 +129,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
        writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
        tmp = readl(&pmc->pcr);
        tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
-       tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) |
+       tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
               AT91_PMC_PCR_CMD_WRITE |
               AT91_PMC_PCR_GCKDIV_(best_div) |
               AT91_PMC_PCR_GCKEN;