arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA

BCM6855 is a Broadcom ARM A7 based PON Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
broadband SoC, this patch adds it under CONFIG_BCM6855 chip config and
CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL101 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from linux.

The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index e86ffc0e3fb58a7806e1736ce2827cbaa8a18375..03fc6c5c283d6f937557cbb8e6d76cad9400d58c 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -229,6 +229,7 @@ N:  bcm[9]?63178
 N:     bcm[9]?6756
 N:     bcm[9]?6813
 N:     bcm[9]?6846
+N:     bcm[9]?6855
 N:     bcm[9]?6856
 N:     bcm[9]?6858
 N:     bcm[9]?6878

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 546a46008c42dc74698ccbe83781929a22a27f7b..68630a7c9ae685c57301fde4edf86d756f7af227 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1193,6 +1193,8 @@ dtb-$(CONFIG_BCM6813) += \
        bcm96813.dtb
 dtb-$(CONFIG_BCM6846) += \
        bcm96846.dtb
+dtb-$(CONFIG_BCM6855) += \
+       bcm96855.dtb
 dtb-$(CONFIG_BCM6856) += \
        bcm96856.dtb \
        bcm968360bg.dtb

diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi
new file mode 100644 (file)
index 0000000..620f51a
--- /dev/null
+++ b/arch/arm/dts/bcm6855.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       compatible = "brcm,bcm6855", "brcm,bcmbca";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               CA7_0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x0>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               CA7_1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x1>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               CA7_2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x2>;
+                       next-level-cache = <&L2_0>;
+                       enable-method = "psci";
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+               arm,cpu-registers-not-fw-configured;
+       };
+
+       pmu: pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
+       };
+
+       clocks: clocks {
+               periph_clk: periph-clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
+
+               uart_clk: uart-clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clocks = <&periph_clk>;
+                       clock-div = <4>;
+                       clock-mult = <1>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       axi@81000000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x81000000 0x8000>;
+
+               gic: interrupt-controller@1000 {
+                       compatible = "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+                       reg = <0x1000 0x1000>,
+                               <0x2000 0x2000>,
+                               <0x4000 0x2000>,
+                               <0x6000 0x2000>;
+               };
+       };
+
+       bus@ff800000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xff800000 0x800000>;
+
+               uart0: serial@12000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0x12000 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&uart_clk>, <&uart_clk>;
+                       clock-names = "uartclk", "apb_pclk";
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts
new file mode 100644 (file)
index 0000000..e4e740c
--- /dev/null
+++ b/arch/arm/dts/bcm96855.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6855.dtsi"
+
+/ {
+       model = "Broadcom BCM96855 Reference Board";
+       compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x08000000>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
index 5b977734df41b6be0769f2db1cc54562c3349ddd..27b243cbc3d8270195ad6ee6e84351bfc6248364 100644 (file)
--- a/arch/arm/mach-bcmbca/Kconfig
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -83,6 +83,16 @@ config BCM6846
        select DM_SERIAL
        select BCM6345_SERIAL
 
+config BCM6855
+       bool "Support for Broadcom 6855 Family"
+       select SYS_ARCH_TIMER
+       select CPU_V7A
+       select DM_SERIAL
+       select PL01X_SERIAL
+       help
+         Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway
+         SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753.
+
 config BCM6856
        bool "Support for Broadcom 6856 Family"
        select ARM64
@@ -121,6 +131,7 @@ source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6813/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6846/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6855/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6856/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6858/Kconfig"
 source "arch/arm/mach-bcmbca/bcm6878/Kconfig"

diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
index c0680941749980e58346864cb9a7ad3f61a6de47..7de9450e1924ea4d104465e0b12ccca896a4ee7e 100644 (file)
--- a/arch/arm/mach-bcmbca/Makefile
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_BCM63178) += bcm63178/
 obj-$(CONFIG_BCM6756) += bcm6756/
 obj-$(CONFIG_BCM6813) += bcm6813/
 obj-$(CONFIG_BCM6846) += bcm6846/
+obj-$(CONFIG_BCM6855) += bcm6855/
 obj-$(CONFIG_BCM6856) += bcm6856/
 obj-$(CONFIG_BCM6858) += bcm6858/
 obj-$(CONFIG_BCM6878) += bcm6878/

diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig
new file mode 100644 (file)
index 0000000..78087c7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6855
+
+config TARGET_BCM96855
+       bool "Broadcom 6855 Reference Board"
+       depends on ARCH_BCMBCA
+
+config SYS_SOC
+       default "bcm6855"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif

diff --git a/arch/arm/mach-bcmbca/bcm6855/Makefile b/arch/arm/mach-bcmbca/bcm6855/Makefile
new file mode 100644 (file)
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o

diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
index 7da9e954d4b26f51ccf6316556e444f0a5ee97b9..5903a6a786fb7b778878ed71e8ebc6df2f90600f 100644 (file)
--- a/board/broadcom/bcmbca/Kconfig
+++ b/board/broadcom/bcmbca/Kconfig
@@ -86,6 +86,13 @@ config SYS_CONFIG_NAME
 
 endif
 
+if TARGET_BCM96855
+
+config SYS_CONFIG_NAME
+       default "bcm96855"
+
+endif
+
 if TARGET_BCM96856
 
 config SYS_CONFIG_NAME

diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig
new file mode 100644 (file)
index 0000000..223c0a1
--- /dev/null
+++ b/configs/bcm96855_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6855=y
+CONFIG_TARGET_BCM96855=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_IDENT_STRING=" Broadcom BCM6855"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y

diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
new file mode 100644 (file)
index 0000000..6e420f2
--- /dev/null
+++ b/include/configs/bcm96855.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96855_H
+#define __BCM96855_H
+
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+
+#endif