]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Convert CONFIG_FSL_MEMAC et al to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 23 Jul 2022 17:05:10 +0000 (13:05 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 4 Aug 2022 20:18:48 +0000 (16:18 -0400)
This converts the following to Kconfig:
   CONFIG_FSL_MEMAC
   CONFIG_SYS_MEMAC_LITTLE_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
44 files changed:
arch/arm/include/asm/arch-fsl-layerscape/config.h
configs/ls1088aqds_defconfig
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
configs/ls1088aqds_qspi_defconfig
configs/ls1088aqds_sdcard_ifc_defconfig
configs/ls1088aqds_sdcard_qspi_defconfig
configs/ls1088aqds_tfa_defconfig
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
configs/ls1088ardb_tfa_defconfig
configs/ls2080aqds_SECURE_BOOT_defconfig
configs/ls2080aqds_defconfig
configs/ls2080aqds_nand_defconfig
configs/ls2080aqds_qspi_defconfig
configs/ls2080aqds_sdcard_defconfig
configs/ls2080ardb_SECURE_BOOT_defconfig
configs/ls2080ardb_defconfig
configs/ls2080ardb_nand_defconfig
configs/ls2081ardb_defconfig
configs/ls2088aqds_tfa_defconfig
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
configs/ls2088ardb_qspi_defconfig
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
configs/ls2088ardb_tfa_defconfig
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
configs/lx2160aqds_tfa_defconfig
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
configs/lx2160ardb_tfa_defconfig
configs/lx2160ardb_tfa_stmm_defconfig
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
configs/lx2162aqds_tfa_defconfig
configs/lx2162aqds_tfa_verified_boot_defconfig
configs/ten64_tfa_defconfig
drivers/net/Kconfig
drivers/net/fm/Makefile
drivers/net/phy/Kconfig
include/configs/ls1088aqds.h
include/configs/ls1088ardb.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/lx2160a_common.h

index f6710d0b0e1ecff90e712e990b554c681ab861b1..76e07f385b3d9daacfe06019144549e3cca33065 100644 (file)
@@ -40,8 +40,6 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                      0x06000000
 #define GICR_BASE                      0x06100000
@@ -49,8 +47,6 @@
 /* SMMU Defintions */
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
-/* DCFG - GUR */
-
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE                    0x04000000
 #define CCI_MN_RNF_NODEID_LIST         0x180
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* DCFG - GUR */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                              0x06000000
 #define GICR_BASE                              0x06200000
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* SEC */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
index bd34f8dff40bf57a31154c42e00491dc09d2ee6d..aca271aa9f5f9fa77b6e3bad5b74e2b39c1bbaa7 100644 (file)
@@ -89,6 +89,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3af10a0e0627bb01d5c21d25bf9bc941f34b287a..9bed029a349fcc5df358ee7ab0fe0258f9e0b80f 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 55a5389272a4d15fdfd948b7adb88badcfd49e25..4a56e43e2bf5f6c700a8d5a9fc96416ccdbe21ab 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3aa20d35af038c8c4cd5d80d161ac792a1fdc7db..d203fb9b13d179653b5f976474b54fb2200cb87c 100644 (file)
@@ -108,6 +108,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index fa1f71d77c1f111d97e412fc319f632fb4750d57..1bd83af1018964c4245bae02b6ed30c7dba1eea6 100644 (file)
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 91899d2ed88bcdd4582fa9cf6b6902dd992439f6..c59de47ab63c0c8088f4b5e59119234512890443 100644 (file)
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b4cae480e17549b4684609fc225eb1c6a6850547..aa9bc8a46c364d5a928d3fdb31fdad6791f48e8e 100644 (file)
@@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 452ee839b87b42127ab19d928544a4501a202d8c..2459212c36f58d06403901452bf7e644ed4e5ba8 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index e36512e62d5502d3137199a93c0b0988ee6292db..fc222b5dd2c3c844cf638d6898932cada735a71d 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 2f81a1343c171eccbb1a6a90f4c26731a1fffad6..eba206dd7bba3a06b358a9e9fc87f485891344e0 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index b5f556dc2035ef0d7d94a51cffca8a5f75c1f537..347cc604105d21a58b227d6a79ea60f33f5a7694 100644 (file)
@@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 3af7828887cdd605e4071638a2d41783fd661960..362b4bea2b531de46a26ac08bc2f90a25c6692ef 100644 (file)
@@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 965863dbd391bb63c0dac159f97c94f9f36d093c..a4143871cb24e075d70d5b1e4759033481e4a3be 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3e0da6884515756123b885825de5ba4b0894f512..91b52265851a3e667c080040281727a64a7c6796 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 1d841af6b0c6f8197a0a0cd141856b4162e6486f..7d3cce0751b093f689153f146cfd91c55681bf61 100644 (file)
@@ -97,6 +97,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 302de323988890bb74c7f3acaa682569de5d82db..6bb37819c17e37dad991778297b33c48ec303a62 100644 (file)
@@ -77,6 +77,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index e97284222dcd820d3290803a4688b724b8515685..e2710b8ec788e732925ed14ff1a02a5b331e277a 100644 (file)
@@ -91,6 +91,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 16367fc453840361669a471e5b022fb27fc2897c..1d0aea08b4a80d328759d925777eab948867bf3d 100644 (file)
@@ -80,6 +80,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 82ad9b27b06eab6b2c6eb591931330577bf906f9..ec6869cf54779769250c46bce5230854433a4f70 100644 (file)
@@ -83,6 +83,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 189a4e0683cfe5a440842e0a1bc516deb113ef41..fa929ac4dab0d9d56e2edd22381c02ef1a47c918 100644 (file)
@@ -102,6 +102,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index fb7faa46d2cb14e24be3b8d2d4bb6343f331ff56..e6e6fe6efc68d093efb953dad25f37e01b08fe2f 100644 (file)
@@ -72,6 +72,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 2eba6b69a7befc64105b16adcb3c203c3c675f7d..2a7cbd3a1bbef129c186fe7b2e5cf03ff19cca89 100644 (file)
@@ -95,6 +95,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b86f8164f0b85a5a42fc94195747bcace6462391..5d9c48b13979f5d005d64cc6458861988591e21c 100644 (file)
@@ -71,6 +71,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 9e08552fb375d41006eb580344da6def57eac24f..0628cc274d7a72ad1d39653f1dc458a1e105eef3 100644 (file)
@@ -78,6 +78,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 0c58a6dd935cb2ebf6f9df0f4ab653cd86f4e226..5fb13460549a45202187be4f9079ec4616ba851c 100644 (file)
@@ -86,6 +86,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index a7c70368377327a36a1dccaf6d39688969b20a82..bf9a016c7e6a3a0aeb488f77d7e1eb24d0e4e917 100644 (file)
@@ -94,6 +94,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index b2bc71afa8ef60c56feca83bb35cbdb86f9c9885..21c60524f4d6919f5baad469f2e0078d013479f5 100644 (file)
@@ -82,6 +82,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 32e47c326e8f2166a210fabc2c7d8e68075167e5..62b214bc0b18cfc8910b89567675fb857bb8cadd 100644 (file)
@@ -89,6 +89,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index a758a4dca2296f652ec207b644180330bef63f47..65e43bf74699d360b809d91015605ae10c96b8bf 100644 (file)
@@ -75,6 +75,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index e6e794006cf63c293a0c1a5df91dcc8a56327dea..8cdebc808e0e23b3a7fce0f89fe4292d0e784599 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bbdcb895d8e4fb614a27bc9faf46acca5e6a4eb1..c7e9afe0a2dd9bcabb91e51f20e083070d666301 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bb81e56fed81811677901ffdbd4b0ca93ab3de41..ca70f8b5cca1f2f4c27bfec4bcdfee0f036e5082 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 216ac800742007fc3383d2251b6adbfa448979de..68cdefb52e4eec14b8c10225fceb407ffad8286f 100644 (file)
@@ -92,6 +92,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b7a4238e92eac6899b42e2634adcb7354427c1a5..ee3134e80c90fc317aba5eb9be38d44e57fc2411 100644 (file)
@@ -93,6 +93,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 4bbee30b064220070f4e2993986bf6c159504d8b..dad6c2d9318d1a7af28dc52dcc2753eb0b5829fa 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 21d6481db9a11cd07f8852c47878a045d2cf5cca..93e7dbe97661f139d765f6f612fd70f8a5e8678e 100644 (file)
@@ -375,6 +375,7 @@ config SYS_QE_FMAN_FW_LENGTH
 
 config SYS_FMAN_V3
        bool
+       select FSL_MEMAC
        help
          SoC has FMan v3 with mEMAC
 
index ae3841217663f20a2141ebf56805b42daaf4f1bd..5a7d3037af405d4960503cec11f04f7dcf358bff 100644 (file)
@@ -11,7 +11,6 @@ obj-y += tgec.o
 obj-y += tgec_phy.o
 
 # Soc have FMAN v3 with mEMAC
-obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
 obj-$(CONFIG_SYS_FMAN_V3) += memac.o
 
 # SoC specific SERDES support
index 33a4b6f30db038c71e2db473c475f5445d221dc7..52ce08b3b3841944d809d41f85bc908404f34caf 100644 (file)
@@ -345,6 +345,13 @@ config PHY_NCSI
 
 endif #PHYLIB
 
+config FSL_MEMAC
+       bool "NXP mEMAC PHY support"
+
+config SYS_MEMAC_LITTLE_ENDIAN
+       bool "mEMAC is access in little endian mode"
+       depends on FSL_MEMAC || FSL_LS_MDIO
+
 config PHY_RESET_DELAY
        int "Extra delay after reset before MII register access"
        default 0
index 6db0ba5f5ae2371980f35b606eba01b0d57f48e2..747ee9d4428a796d4fdfd72a37194420d4937fa5 100644 (file)
 #endif
 #endif
 
-#define CONFIG_FSL_MEMAC
-
 #define COMMON_ENV \
        "kernelheader_addr_r=0x80200000\0"      \
        "fdtheader_addr_r=0x80100000\0"         \
 #endif
 
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
index c3e87ed24db9c4ed49c0a58cef5f4e4811070e72..3e829ea8659a147d73301b5ede4e80373abbd995 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM              0
 
-#define CONFIG_FSL_MEMAC
-
 #ifndef SPL_NO_ENV
 /* Initial environment variables */
 #ifdef CONFIG_TFABOOT
index f6efda258c0e1b52dd17e44a7d088b10412ef7f3..6487397f65286ecbbed3329294cacfd54f37e9da 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #ifdef CONFIG_NXP_ESBC
 #endif
 
 #if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_FSL_MEMAC
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
index c6b601de227a234d3091fe42cbaa59ccb62a6417..87d07b765c6c53c978642cdad81aeb17a146670b 100644 (file)
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 #define BOOT_TARGET_DEVICES(func) \
        func(USB, usb, 0) \
        func(MMC, mmc, 0) \
index b7543731691fc41a70eec82d40e1b781eb481973..0f5b0444e70f829ad45bf61d5a6a62e0642c9fdb 100644 (file)
@@ -10,8 +10,6 @@
 #include <asm/arch/config.h>
 #include <asm/arch/soc.h>
 
-#define CONFIG_FSL_MEMAC
-
 #define CONFIG_SYS_FLASH_BASE          0x20000000
 
 /* DDR */