CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_COUNT=0x80
CONFIG_MTD=y
CONFIG_SYS_MTDPARTS_RUNTIME=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
SPL-NAND driver with software ECC correction support.
- CONFIG_NAND_OMAP_ECCSCHEME
- On OMAP platforms, this CONFIG specifies NAND ECC scheme.
- It can take following values:
- OMAP_ECC_HAM1_CODE_SW
- 1-bit Hamming code using software lib.
- (for legacy devices only)
- OMAP_ECC_HAM1_CODE_HW
- 1-bit Hamming code using GPMC hardware.
- (for legacy devices only)
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
- 4-bit BCH code (unsupported)
- OMAP_ECC_BCH4_CODE_HW
- 4-bit BCH code (unsupported)
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
- 8-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using software library.
- - requires CONFIG_BCH to enable software BCH library
- (For legacy device which do not have ELM h/w engine)
- OMAP_ECC_BCH8_CODE_HW
- 8-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using ELM hardware engine.
- OMAP_ECC_BCH16_CODE_HW
- 16-bit BCH code with
- - ecc calculation using GPMC hardware engine,
- - error detection using ELM hardware engine.
-
- How to select ECC scheme on OMAP and AMxx platforms ?
- -----------------------------------------------------
- Though higher ECC schemes have more capability to detect and correct
- bit-flips, but still selection of ECC scheme is dependent on following
- - hardware engines present in SoC.
- Some legacy OMAP SoC do not have ELM h/w engine thus such
- SoC cannot support BCHx_HW ECC schemes.
- - size of OOB/Spare region
- With higher ECC schemes, more OOB/Spare area is required to
- store ECC. So choice of ECC scheme is limited by NAND oobsize.
-
- In general following expression can help:
- NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
- where
- NAND_OOBSIZE = number of bytes available in
- OOB/spare area per NAND page.
- NAND_PAGESIZE = bytes in main-area of NAND page.
- ECC_BYTES = number of ECC bytes generated to
- protect 512 bytes of data, which is:
- 3 for HAM1_xx ecc schemes
- 7 for BCH4_xx ecc schemes
- 14 for BCH8_xx ecc schemes
- 26 for BCH16_xx ecc schemes
-
- example to check for BCH16 on 2K page NAND
- NAND_PAGESIZE = 2048
- NAND_OOBSIZE = 64
- 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
- Thus BCH16 cannot be supported on 2K page NAND.
-
- However, for 4K pagesize NAND
- NAND_PAGESIZE = 4096
- NAND_OOBSIZE = 224
- ECC_BYTES = 26
- 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
- Thus BCH16 can be supported on 4K page NAND.
-
-
CONFIG_NAND_OMAP_GPMC_PREFETCH
On OMAP platforms that use the GPMC controller
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
and BCH16 ECC algorithms.
+if NAND_OMAP_GPMC
+
config NAND_OMAP_GPMC_PREFETCH
bool "Enable GPMC Prefetch"
- depends on NAND_OMAP_GPMC
default y
help
On OMAP platforms that use the GPMC controller
config NAND_OMAP_ELM
bool "Enable ELM driver for OMAPxx and AMxx platforms."
- depends on NAND_OMAP_GPMC && !OMAP34XX
+ depends on !OMAP34XX
help
ELM controller is used for ECC error detection (not ECC calculation)
of BCH4, BCH8 and BCH16 ECC algorithms.
detection. However ECC calculation on such plaforms would still be
done by GPMC controller.
+choice
+ prompt "ECC scheme"
+ default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ help
+ On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+ It can take following values:
+ OMAP_ECC_HAM1_CODE_SW
+ 1-bit Hamming code using software lib.
+ (for legacy devices only)
+ OMAP_ECC_HAM1_CODE_HW
+ 1-bit Hamming code using GPMC hardware.
+ (for legacy devices only)
+ OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH4_CODE_HW
+ 4-bit BCH code (unsupported)
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using software library.
+ - requires CONFIG_BCH to enable software BCH library
+ (For legacy device which do not have ELM h/w engine)
+ OMAP_ECC_BCH8_CODE_HW
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+ OMAP_ECC_BCH16_CODE_HW
+ 16-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+ How to select ECC scheme on OMAP and AMxx platforms ?
+ -----------------------------------------------------
+ Though higher ECC schemes have more capability to detect and correct
+ bit-flips, but still selection of ECC scheme is dependent on following
+ - hardware engines present in SoC.
+ Some legacy OMAP SoC do not have ELM h/w engine thus such
+ SoC cannot support BCHx_HW ECC schemes.
+ - size of OOB/Spare region
+ With higher ECC schemes, more OOB/Spare area is required to
+ store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+ In general following expression can help:
+ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+ where
+ NAND_OOBSIZE = number of bytes available in
+ OOB/spare area per NAND page.
+ NAND_PAGESIZE = bytes in main-area of NAND page.
+ ECC_BYTES = number of ECC bytes generated to
+ protect 512 bytes of data, which is:
+ 3 for HAM1_xx ecc schemes
+ 7 for BCH4_xx ecc schemes
+ 14 for BCH8_xx ecc schemes
+ 26 for BCH16_xx ecc schemes
+
+ example to check for BCH16 on 2K page NAND
+ NAND_PAGESIZE = 2048
+ NAND_OOBSIZE = 64
+ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+ Thus BCH16 cannot be supported on 2K page NAND.
+
+ However, for 4K pagesize NAND
+ NAND_PAGESIZE = 4096
+ NAND_OOBSIZE = 224
+ ECC_BYTES = 26
+ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+ Thus BCH16 can be supported on 4K page NAND.
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ bool "1-bit Hamming code using software lib"
+
+config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ bool "1-bit Hamming code using GPMC hardware"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ bool "8-bit BCH code with HW calculation SW error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ bool "8-bit BCH code with HW calculation and error detection"
+
+config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ bool "16-bit BCH code with HW calculation and error detection"
+
+endchoice
+
+config NAND_OMAP_ECCSCHEME
+ int
+ default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
+ default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
+ default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
+ default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
+ default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
+ help
+ This must be kept in sync with the enum in
+ include/linux/mtd/omap_gpmc.h
+
+endif
+
config NAND_VF610_NFC
bool "Support for Freescale NFC for VF610"
select SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define MTDIDS_DEFAULT "nand0=nand.0"
#endif /* CONFIG_MTD_RAW_NAND */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#endif /* ! __CONFIG_IGEP003X_H */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#endif
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x8000000
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
/* NAND: SPL related configs */
/* USB configuration */
/* NAND support */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
/* NAND specific changes for etamin due to different page size */
#undef CONFIG_SYS_NAND_ECCPOS
#undef CONFIG_SYS_ENV_SECT_SIZE
-#undef CONFIG_NAND_OMAP_ECCSCHEME
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#endif /* __IGEP00X0_H */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#endif
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_ECCSTEPS 4
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
/* SPL */
/* Defines for SPL */