]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
mpc83xx: Normalize BR/OR option lines
authorMario Six <mario.six@gdsys.cc>
Mon, 21 Jan 2019 08:17:59 +0000 (09:17 +0100)
committerMario Six <mario.six@gdsys.cc>
Tue, 21 May 2019 05:52:33 +0000 (07:52 +0200)
All BR/OR option lines should have the same layout to make them easier
to migrate to Kconfig. This includes using the same option macros
everywhere.

The normalize the lines,
* replace function macros with their results, and
* replace hardcoded hex values with standard macros

Signed-off-by: Mario Six <mario.six@gdsys.cc>
27 files changed:
include/configs/MPC8308RDB.h
include/configs/MPC8313ERDB_NAND.h
include/configs/MPC8313ERDB_NOR.h
include/configs/MPC8323ERDB.h
include/configs/MPC832XEMDS.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349EMDS_SDRAM.h
include/configs/MPC8349ITX.h
include/configs/MPC837XEMDS.h
include/configs/MPC837XERDB.h
include/configs/caddy2.h
include/configs/hrcon.h
include/configs/ids8313.h
include/configs/kmcoge5ne.h
include/configs/kmeter1.h
include/configs/kmopti2.h
include/configs/kmsupx5.h
include/configs/kmtegr1.h
include/configs/kmtepr2.h
include/configs/kmvect1.h
include/configs/mpc8308_p1m.h
include/configs/sbc8349.h
include/configs/strider.h
include/configs/suvd3.h
include/configs/tuge1.h
include/configs/tuxx1.h
include/configs/vme8349.h

index 1953d18e8780fd2cc6053d02d119dccf8b993dbe..e19bcafd5cead364f817681b62d2fa715a2d6813 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | BR_PS_8               /* 8 bit Port */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
                                        /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_XACS \
                                        | OR_GPCM_SCY_15 \
index 79c7f12baeeb2ab1aab89189628bee907467e9e9..bbb9d4b936cb2d45e26f2835498f9a0da1f66227 100644 (file)
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
                                        /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV2 \
                                        | OR_GPCM_XACS \
                                        | BR_PS_8       /* 8 bit port */ \
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_XACS \
                                        | OR_GPCM_SCY_15 \
index 1b2bba96d33c0d174c5214de5e756dd729fd4ee3..1cb001864a4e7b1a6e6352292912746be5fd4784 100644 (file)
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
                                        /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV2 \
                                        | OR_GPCM_XACS \
                                        | BR_PS_8       /* 8 bit port */ \
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_XACS \
                                        | OR_GPCM_SCY_15 \
index cb17c7644de6a32180c994eda70459e2fc3568b6..30f1e4453d167f83534733db92302cfda32cc265 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
                                | OR_GPCM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index d51d5ce06d5b30139870abe133864fb676d0918f..3a8a3e4fb89875479587de2677f7936a2aa47ca8 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
                                | OR_GPCM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | BR_MS_GPCM \
                                | BR_V)
                                /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB \
                                | OR_GPCM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_XACS \
                                | BR_MS_GPCM \
                                | BR_V)
                                /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
                                | OR_GPCM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_XACS \
index 06017a81bc883681daf858fdd8a51c9a7696cd86..fa73b81c3a0b96f4fb98bf1e8509d149c39b3c00 100644 (file)
                                | BR_PS_16      /* 16 bit port  */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index 708a21f1649c3098c62d014c911ef33986a18214..218c4b1fc98a52b4853c250b24df83d55e7d3421 100644 (file)
                                | BR_PS_16      /* 16 bit port  */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index 16d615dcc65fe44127c6de8d2dacd91290a5b0a8..0bf179a70b146a21b1b9033a719b72a8255b49c1 100644 (file)
@@ -217,7 +217,7 @@ boards, we say we have two, but don't display a message if we find only one. */
                                | BR_PS_16 \
                                | BR_MS_GPCM \
                                | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index 9d6dc767ef33b18fe910cf6d6cdb924555689de3..e10c58d7eda5c8d53a3c29e85823399370d2909a 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index a1de8acc5c794e43fc67bb5d69647e179476a21f..1e45b5ee3f159615ff443e654ad237e40b8eb329 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_9 \
                                | OR_GPCM_EHTR_SET \
index b355e56355f42db7de35ef956da0418c0b8daad9..ffd52a200a32c2ae2c640432e2c830c7175e89bf 100644 (file)
@@ -74,7 +74,7 @@
                                         BR_MS_GPCM |   /*  MSEL = GPCM */ \
                                         BR_V)          /* valid */
 
-#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_4MB \
                                        | OR_GPCM_XAM \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV2 \
index d86de800db76c3f21bb30cb6db4e7f61f4b2c3ae..4193ceb3793f14c5cb8637c20007c95cff350880 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_1MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index e930c65637be8d4c839e59c6fc27c74ab4b44047..871b91f2183effc1bf57491fe3fbf3b0076d6710 100644 (file)
                                         BR_MS_GPCM |\
                                         BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB |\
                                         OR_GPCM_SCY_10 |\
                                         OR_GPCM_EHTR |\
                                         OR_GPCM_TRLX |\
 #define NAND_CACHE_PAGES               64
 
 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE) |\
-                                (2<<BR_DECC_SHIFT) |\
+                                BR_DECC_CHK_GEN |\
                                 BR_PS_8 |\
                                 BR_MS_FCM |\
                                 BR_V)
 
-#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000 |\
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB |\
                                 OR_FCM_PGS |\
                                 OR_FCM_CSCT |\
                                 OR_FCM_CST |\
                                         BR_MS_GPCM |\
                                         BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM          0xFFFE0C74
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
 
 /*
  * CPLD setup
                                         BR_MS_GPCM |\
                                         BR_V)
 
-#define CONFIG_SYS_OR3_PRELIM          0xFFFF8814
+#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
 
 /*
  * HW-Watchdog
index dcabac5666514d20fbd7c3a04b54677bd4f174bc..370e6b496aea24838bdf228dd6564b0b9e41e4b3 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_BR3_PRELIM (\
        CONFIG_SYS_PAXE_BASE | \
-       (1 << BR_PS_SHIFT) | \
+       BR_PS_8 | \
        BR_V)
 
 #define CONFIG_SYS_OR3_PRELIM (\
-       MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+       OR_AM_256MB | \
        OR_GPCM_CSNT | \
        OR_GPCM_ACS_DIV2 | \
        OR_GPCM_SCY_2 | \
 
 #define CONFIG_SYS_BR4_PRELIM (\
        CONFIG_SYS_BFTIC3_BASE |\
-       (1 << BR_PS_SHIFT) | \
+       BR_PS_8 | \
        BR_V)
 
 #define CONFIG_SYS_OR4_PRELIM (\
-       MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
+       OR_AM_256MB|\
        OR_GPCM_CSNT | \
        OR_GPCM_ACS_DIV2 |\
        OR_GPCM_SCY_2 |\
index 1da8df393126431b1a7179ec578c0fc01ae33584..2650544305c731e1634a3d662a927a7b79b152a1 100644 (file)
@@ -98,7 +98,7 @@
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_BR3_PRELIM (\
        CONFIG_SYS_PAXE_BASE | \
-       (1 << BR_PS_SHIFT) | \
+       BR_PS_8 | \
        BR_V)
 
 #define CONFIG_SYS_OR3_PRELIM (\
-       MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+       OR_AM_256MB | \
        OR_GPCM_CSNT | \
        OR_GPCM_ACS_DIV2 | \
        OR_GPCM_SCY_2 | \
index e732c2ad022d784b7def1f36500011139bbba69f..6e59fde6bd0736e8c04b2362ccc1766d386d03ec 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
                                 BR_PS_16 |             \
                                 BR_MS_GPCM |           \
                                 BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_SCY_4 | \
                                 OR_GPCM_TRLX_CLEAR | \
                                 OR_GPCM_EHTR_CLEAR)
index 42fbdbf947f4e7bed24fb80b2fcb66dc827d57dd..af39e8bb857e1046b50cce305feadd4e1c07bf6a 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
index 222eb72f8eb593a7ac0960519d41590c08917ab7..1312aa2fa998b4933ef989551002c9e33d0168a1 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
                                 OR_GPCM_SCY_5 | \
                                 OR_GPCM_TRLX_CLEAR | \
                                 OR_GPCM_EHTR_CLEAR)
index e542158022ad735d57720e57accb95918d8c1cce..fd00ea86a98883c6a594e016123c004c78f3bdef 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
                                 BR_PS_16 |             \
                                 BR_MS_GPCM |           \
                                 BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_SCY_4 | \
                                 OR_GPCM_TRLX_CLEAR | \
                                 OR_GPCM_EHTR_CLEAR)
index 3e2cc60f3ede525c3f2b88154306446e9bf03502..3d9164714c7725634a1ba0f16d81074a98f5f3f8 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_PS_16 | \
                                 BR_MS_UPMA | \
                                 BR_V)
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB)
 
 #define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
                                 BR_PS_16 | \
                                 BR_V)
 
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_3 | \
index aa9710f9c21647ebc902d0fd68ad974f7fe09a83..046355f64547d7bb2c0807ef039aec3dee8a7407 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_64MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
index edf76e58519429a9800e33b67460ffb369a22c3b..dffb7c61086571f7d1bab892bc1b11c2167db1d8 100644 (file)
                                        | BR_MS_GPCM    /* MSEL = GPCM */ \
                                        | BR_V)         /* valid */
 
-#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB \
                                        | OR_GPCM_XAM \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV2 \
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_64MB \
                        | OR_SDRAM_XAM \
                        | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
                        | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
index 3b0207488f4aa629518193684329b41bb3fec759..184396e0379ced3af93e4916b20d418d6bf4ce13 100644 (file)
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
 
-#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+#define CONFIG_SYS_OR1_PRELIM   (OR_AM_1MB \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_SCY_5 \
index 987b2d77cc1e3d043cd6266ed0fe31ce81221274..ad270de87d736f7daf8fc7cee273427d1ad2e4dc 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_PS_16 | \
                                 BR_MS_UPMA | \
                                 BR_V)
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB)
 
 #define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
                                 BR_PS_16 | \
                                 BR_V)
 
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_3 | \
index 5fceac7ae16db50b50a10c2627b3540429ed1101..af6a348ba579cebc965eda8c118f062cab31e694 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
index 1b97d0fecbd7aaba703da69b4ff9bb0ecbb59643..18476c12de29192e229481bc87a930ff6e39ab5d 100644 (file)
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
 
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_5 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                BR_PS_8 | /* 8 bit port size */ \
                                BR_MS_GPCM | /* MSEL = GPCM */ \
                                BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_SCY_2 | \
                                OR_GPCM_TRLX_SET | OR_GPCM_EAD)
                                 BR_MS_GPCM | \
                                 BR_V)
 
-#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV4 | \
                                 OR_GPCM_SCY_2 | \
                                 BR_MS_GPCM |           \
                                 BR_V)
 
-#define CONFIG_SYS_OR3_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
                                 OR_GPCM_CSNT | \
                                 OR_GPCM_ACS_DIV2 | \
                                 OR_GPCM_SCY_2 | \
index ed02661f82a08030e7d646f8136a5272bec58b7f..76821e7a407a74194a7e09e59868fc5997f293a3 100644 (file)
@@ -74,7 +74,7 @@
                                         BR_MS_GPCM |   /*  MSEL = GPCM */ \
                                         BR_V)          /* valid */
 
-#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_128MB \
                                        | OR_GPCM_XAM \
                                        | OR_GPCM_CSNT \
                                        | OR_GPCM_ACS_DIV2 \