driver/ddr/freescale: Fix DDR3 driver for ARM

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9aec2ae7a08b103aa41367887140d759f71c..59f2fd661096964a79c4edcc302084c39a7adf80 100644 (file)
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@ step2:
         * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
         * Let's wait for 800ms
         */
-       bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+       bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
                        >> SDRAM_CFG_DBW_SHIFT);
        timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
                (get_ddr_freq(0) >> 20)) << 1;