]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev Kit
authorAdam Ford <aford173@gmail.com>
Tue, 30 Jun 2020 14:30:11 +0000 (09:30 -0500)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Sat, 25 Jul 2020 12:19:26 +0000 (14:19 +0200)
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also
known as the RZ/G2M.

The kit consists of a SOM + Baseboard and supports microSD,
eMMC, Ethernet, a couple celular radios, two CAN interfaces,
Bluetooth and WiFi.

Signed-off-by: Adam Ford <aford173@gmail.com>
12 files changed:
arch/arm/dts/Makefile
arch/arm/dts/beacon-renesom-baseboard.dtsi [new file with mode: 0644]
arch/arm/dts/beacon-renesom-som.dtsi [new file with mode: 0644]
arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts [new file with mode: 0644]
arch/arm/mach-rmobile/Kconfig.64
board/beacon/beacon-rzg2m/Kconfig [new file with mode: 0644]
board/beacon/beacon-rzg2m/MAINTAINERS [new file with mode: 0644]
board/beacon/beacon-rzg2m/Makefile [new file with mode: 0644]
board/beacon/beacon-rzg2m/beacon-rzg2m.c [new file with mode: 0644]
configs/r8a774a1_beacon_defconfig [new file with mode: 0644]
include/configs/beacon-rzg2m.h [new file with mode: 0644]

index 5726156a2ddd268852df081d59d5186c9b240f23..f01eb7bf5fc4f40fd2b21b80cccdfaf2f7a37a6b 100644 (file)
@@ -774,6 +774,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
        r8a7794-silk-u-boot.dtb
 
 dtb-$(CONFIG_RCAR_GEN3) += \
+       r8a774a1-beacon-rzg2m-kit.dtb \
        r8a77950-ulcb-u-boot.dtb \
        r8a77950-salvator-x-u-boot.dtb \
        r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi
new file mode 100644 (file)
index 0000000..8a472c0
--- /dev/null
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Compass Electronics Group, LLC
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       aliases {
+               serial0 = &scif2;
+               serial1 = &hscif0;
+               serial2 = &hscif1;
+               serial3 = &scif0;
+               serial4 = &hscif2;
+               serial5 = &scif5;
+               spi0 = &msiof0;
+               spi1 = &msiof1;
+               spi2 = &msiof2;
+               spi3 = &msiof3;
+               ethernet0 = &avb;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               power-supply = <&reg_lcd>;
+               enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
+               pwms = <&pwm0 0 50000>;
+               brightness-levels = <0 4 8 16 32 64 128 255>;
+               default-brightness-level = <6>;
+       };
+
+       hdmi0-out {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi0_con: endpoint {
+                               remote-endpoint = <&rcar_dw_hdmi0_out>;
+                       };
+               };
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               key-1 {
+                       gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_1>;
+                       label = "Switch-1";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-2 {
+                       gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_2>;
+                       label = "Switch-2";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-3 {
+                       gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_3>;
+                       label = "Switch-3";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-4 {
+                       gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_4>;
+                       label = "Switch-4";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+               key-5 {
+                       gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_5>;
+                       label = "Switch-4";
+                       wakeup-source;
+                       debounce-interval = <20>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-0 = <&led_pins>;
+               pinctrl-names = "default";
+
+               led0 {
+                       gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+                       label = "LED0";
+                       linux,default-trigger = "heartbeat";
+               };
+               led1 {
+                       gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+                       label = "LED1";
+                       linux,default-trigger = "heartbeat";
+               };
+               led2 {
+                       gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+                       label = "LED2";
+                       linux,default-trigger = "heartbeat";
+               };
+               led3 {
+                       gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+                       label = "LED3";
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_audio: regulator_audio {
+               compatible = "regulator-fixed";
+               regulator-name = "audio-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_lcd: regulator-lcd {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd_panel_pwr";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_lcd_reset: regulator-lcd-reset {
+               compatible = "regulator-fixed";
+               regulator-name = "nLCD_RESET";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               vin-supply = <&reg_lcd>;
+       };
+
+       reg_cam0: regulator_camera {
+               compatible = "regulator-fixed";
+               regulator-name = "reg_cam0";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_cam1: regulator_camera {
+               compatible = "regulator-fixed";
+               regulator-name = "reg_cam1";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               startup-delay-us = <100000>;
+       };
+
+       sound_card {
+               compatible = "audio-graph-card";
+               label = "rcar-sound";
+               dais = <&rsnd_port0>, <&rsnd_port1>;
+       };
+
+       vccq_sdhi0: regulator-vccq-sdhi0 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI0 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1>, <1800000 0>;
+               regulator-always-on;
+       };
+
+       /* External DU dot clocks */
+       x302_clk: x302-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <33000000>;
+       };
+
+       x304_clk: x304-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+};
+
+&audio_clk_a {
+       clock-frequency = <22579200>;
+};
+
+&audio_clk_b {
+       clock-frequency = <22579200>;
+};
+
+&can0 {
+       pinctrl-0 = <&can0_pins>;
+       pinctrl-names = "default";
+       renesas,can-clock-select = <0x0>;
+       status = "okay";
+};
+
+&can1 {
+       pinctrl-0 = <&can1_pins>;
+       pinctrl-names = "default";
+       renesas,can-clock-select = <0x0>;
+       status = "okay";
+};
+
+&du {
+       pinctrl-0 = <&du_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 724>,
+               <&cpg CPG_MOD 723>,
+               <&cpg CPG_MOD 722>,
+               <&versaclock5 1>,
+               <&x302_clk>,
+               <&versaclock5 2>;
+       clock-names = "du.0", "du.1", "du.2",
+               "dclkin.0", "dclkin.1", "dclkin.2";
+};
+
+&ehci0 {
+       dr_mode = "otg";
+       status = "okay";
+       clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>;
+};
+
+&ehci1 {
+       status = "okay";
+       clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>;
+};
+
+&hdmi0 {
+       status = "okay";
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               port@0 {
+                       reg = <0>;
+                       dw_hdmi0_in: endpoint {
+                               remote-endpoint = <&du_out_hdmi0>;
+                       };
+               };
+               port@1 {
+                       reg = <1>;
+                       rcar_dw_hdmi0_out: endpoint {
+                               remote-endpoint = <&hdmi0_con>;
+                       };
+               };
+               port@2 {
+                       /* HDMI sound */
+                       reg = <2>;
+                       dw_hdmi0_snd_in: endpoint {
+                               remote-endpoint = <&rsnd_endpoint1>;
+                       };
+               };
+       };
+};
+
+&hscif1 {
+       pinctrl-0 = <&hscif1_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&hsusb {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&i2c2 {
+       status = "okay";
+       clock-frequency = <100000>;
+       pinctrl-0 = <&i2c2_pins>;
+       pinctrl-names = "default";
+
+       gpio_exp2: gpio@21 {
+               compatible = "onnn,pca9654";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       gpio_exp3: gpio@22 {
+               compatible = "onnn,pca9654";
+               reg = <0x22>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       versaclock6_bb: versaclock6_bb@6a {
+               compatible = "idt,5p49v6965";
+               reg = <0x6a>;
+               #clock-cells = <1>;
+               clocks = <&x304_clk>;
+               clock-names = "xin";
+               /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
+               assigned-clocks = <&versaclock6_bb 1>,
+                                  <&versaclock6_bb 2>,
+                                  <&versaclock6_bb 3>,
+                                  <&versaclock6_bb 4>;
+               assigned-clock-rates =  <24000000>, <24000000>, <24000000>, <24000000>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       pinctrl-0 = <&i2c0_pins>;
+       pinctrl-names = "default";
+};
+
+&i2c5 {
+       status = "okay";
+       clock-frequency = <100000>;
+       pinctrl-0 = <&i2c5_pins>;
+       pinctrl-names = "default";
+
+       codec: wm8962@1a {
+               compatible = "wlf,wm8962";
+               reg = <0x1a>;
+               DCVDD-supply = <&reg_audio>;
+               DBVDD-supply = <&reg_audio>;
+               AVDD-supply = <&reg_audio>;
+               CPVDD-supply = <&reg_audio>;
+               MICVDD-supply = <&reg_audio>;
+               PLLVDD-supply = <&reg_audio>;
+               SPKVDD1-supply = <&reg_audio>;
+               SPKVDD2-supply = <&reg_audio>;
+               gpio-cfg = <
+                       0x0000 /* 0:Default */
+                       0x0000 /* 1:Default */
+                       0x0000 /* 2:Default */
+                       0x0000 /* 3:Default */
+                       0x0000 /* 4:Default */
+                       0x0000 /* 5:Default */
+               >;
+               port {
+                       wm8962_endpoint: endpoint {
+                               remote-endpoint = <&rsnd_endpoint0>;
+                       };
+               };
+       };
+
+       /* 0 - lcd_reset */
+       /* 1 - lcd_pwr */
+       /* 2 - lcd_select */
+       /* 3 - backlight-enable */
+       /* 4 - Touch_shdwn */
+       /* 5 - LCD_H_pol */
+       /* 6 - lcd_V_pol */
+       gpio_exp1: gpio@20 {
+               compatible = "onnn,pca9654";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       touchscreen@26 {
+               compatible = "ilitek,ili2117";
+               reg = <0x26>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+               wakeup-source;
+       };
+};
+
+&ohci0 {
+       dr_mode = "otg";
+       status = "okay";
+};
+
+&ohci1 {
+       status = "okay";
+};
+
+&pciec0 {
+       status = "okay";
+};
+
+&pciec1 {
+       status = "okay";
+};
+
+&pcie_bus_clk {
+       clock-frequency = <100000000>;
+};
+
+&pfc {
+       can0_pins: can0 {
+               groups = "can0_data_a";
+               function = "can0";
+       };
+
+       can1_pins: can1 {
+               groups = "can1_data";
+               function = "can1";
+       };
+
+       du_pins: du {
+               groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp";
+               function = "du";
+       };
+
+       i2c2_pins: i2c2 {
+               groups = "i2c2_a";
+               function = "i2c2";
+       };
+
+       i2c5_pins: i2c5 {
+               groups = "i2c5";
+               function = "i2c5";
+       };
+
+       led_pins: leds {
+               /* GP_0_4 , AVS1, AVS2, GP_7_3 */
+               pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3";
+               bias-pull-down;
+       };
+
+       msiof1_pins: msiof1 {
+               groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g";
+               function = "msiof1";
+       };
+
+       pwm0_pins: pwm0 {
+               groups = "pwm0";
+               function = "pwm0";
+       };
+
+       sdhi0_pins: sd0 {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <3300>;
+       };
+
+       sdhi0_pins_uhs: sd0_uhs {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <1800>;
+       };
+
+       sound_pins: sound {
+               groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+               function = "ssi";
+       };
+
+       sound_clk_pins: sound_clk {
+               groups = "audio_clk_a_a";
+               function = "audio_clk";
+       };
+
+       usb0_pins: usb0 {
+               mux {
+                       groups = "usb0";
+                       function = "usb0";
+               };
+       };
+
+       usb1_pins: usb1 {
+               mux {
+                       groups = "usb1";
+                       function = "usb1";
+               };
+       };
+
+       usb30_pins: usb30 {
+               mux {
+                       groups = "usb30";
+                       function = "usb30";
+               };
+       };
+};
+
+&pwm0 {
+       pinctrl-0 = <&pwm0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&rcar_sound {
+       pinctrl-0 = <&sound_pins &sound_clk_pins>;
+       pinctrl-names = "default";
+
+       /* Single DAI */
+       #sound-dai-cells = <0>;
+
+       /* audio_clkout0/1/2/3 */
+       #clock-cells = <1>;
+       clock-frequency = <11289600>;
+
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 1005>,
+                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               rsnd_port0: port@0 {
+                       reg = <0>;
+                       rsnd_endpoint0: endpoint {
+                               remote-endpoint = <&wm8962_endpoint>;
+
+                               dai-format = "i2s";
+                               bitclock-master = <&rsnd_endpoint0>;
+                               frame-master = <&rsnd_endpoint0>;
+
+                               playback = <&ssi1 &dvc1 &src1>;
+                               capture = <&ssi0>;
+                       };
+               };
+               rsnd_port1: port@1 {
+                   reg = <0x01>;
+                       rsnd_endpoint1: endpoint {
+                               remote-endpoint = <&dw_hdmi0_snd_in>;
+
+                               dai-format = "i2s";
+                               bitclock-master = <&rsnd_endpoint1>;
+                               frame-master = <&rsnd_endpoint1>;
+
+                               playback = <&ssi2>;
+                       };
+               };
+       };
+};
+
+&scif0 {
+       pinctrl-0 = <&scif0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&scif5 {
+       pinctrl-0 = <&scif5_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+       pinctrl-0 = <&sdhi0_pins>;
+       pinctrl-1 = <&sdhi0_pins_uhs>;
+       pinctrl-names = "default", "state_uhs";
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&vccq_sdhi0>;
+       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+       bus-width = <4>;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&ssi1 {
+       shared-pin;
+};
+
+&usb2_phy0 {
+       pinctrl-0 = <&usb0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&usb2_phy1 {
+       pinctrl-0 = <&usb1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi
new file mode 100644 (file)
index 0000000..6c16a27
--- /dev/null
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Compass Electronics Group, LLC
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       memory@48000000 {
+               device_type = "memory";
+               /* first 128MB is reserved for secure area. */
+               reg = <0x0 0x48000000 0x0 0x78000000>;
+       };
+
+       memory@600000000 {
+               device_type = "memory";
+               reg = <0x6 0x00000000 0x0 0x80000000>;
+       };
+
+       osc_32k: osc_32k {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "osc_32k";
+       };
+
+       reg_1p8v: regulator0 {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator1 {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       wlan_pwrseq: wlan_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
+               clocks = <&osc_32k>;
+               clock-names = "ext_clock";
+               post-power-on-delay-ms = <80>;
+       };
+};
+
+&avb {
+       pinctrl-0 = <&avb_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&extal_clk {
+       clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+       clock-frequency = <32768>;
+};
+
+&gpio6 {
+       usb_hub_reset {
+               gpio-hog;
+               gpios = <10 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "usb-hub-reset";
+       };
+};
+
+&hscif0 {
+       pinctrl-0 = <&hscif0_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+       status = "okay";
+       max-speed = <4000000>;
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
+               host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+               device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
+               clocks = <&osc_32k>;
+               clock-names = "extclk";
+       };
+};
+
+&hscif2 {
+       status = "okay";
+       pinctrl-0 = <&hscif2_pins>;
+       pinctrl-names = "default";
+};
+
+&i2c4 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       pca9654: gpio@20 {
+               compatible = "onnn,pca9654";
+               reg = <0x20>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names =
+                       "i2c4_20_0",
+                       "wl_reg_on",
+                       "bt_reg_on",
+                       "i2c4_20_3",
+                       "i2c4_20_4",
+                       "bt_dev_wake",
+                       "i2c4_20_6",
+                       "i2c4_20_7";
+       };
+
+       pca9654_lte: gpio@21 {
+               compatible = "onnn,pca9654";
+               reg = <0x21>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names =
+                       "i2c4_21_0",
+                       "zoe_pwr_on",
+                       "zoe_extint",
+                       "zoe_reset_n",
+                       "sara_reset",
+                       "i2c4_21_5",
+                       "sara_pwr_off",
+                       "sara_networking_status";
+       };
+
+       eeprom@50 {
+               compatible = "microchip, at24c64", "atmel,24c64";
+               pagesize = <32>;
+               read-only;      /* Manufacturing EEPROM programmed at factory */
+               reg = <0x50>;
+       };
+
+       rtc@51 {
+               compatible = "nxp,pcf85263";
+               reg = <0x51>;
+       };
+
+       versaclock5: versaclock_som@6a {
+               compatible = "idt,5p49v6965";
+               reg = <0x6a>;
+               #clock-cells = <1>;
+               clocks = <&x304_clk>;
+               clock-names = "xin";
+               /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
+               assigned-clocks = <&versaclock5 1>,
+                                  <&versaclock5 2>,
+                                  <&versaclock5 3>,
+                                  <&versaclock5 4>;
+               assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
+       };
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       avb_pins: avb {
+               mux {
+                       groups = "avb_link", "avb_mdio", "avb_mii";
+                       function = "avb";
+               };
+
+               pins_mdio {
+                       groups = "avb_mdio";
+                       drive-strength = <24>;
+               };
+
+               pins_mii_tx {
+                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+                       drive-strength = <12>;
+               };
+       };
+
+       scif2_pins: scif2 {
+               groups = "scif2_data_a";
+               function = "scif2";
+       };
+
+       hscif0_pins: hscif0 {
+               groups = "hscif0_data", "hscif0_ctrl";
+               function = "hscif0";
+       };
+
+       hscif1_pins: hscif1 {
+               groups = "hscif1_data_a", "hscif1_ctrl_a";
+               function = "hscif1";
+       };
+
+       hscif2_pins: hscif2 {
+               groups = "hscif2_data_a";
+               function = "hscif2";
+       };
+
+       scif0_pins: scif0 {
+               groups = "scif0_data";
+               function = "scif0";
+       };
+
+       scif5_pins: scif5 {
+               groups = "scif5_data_a";
+               function = "scif5";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk_a";
+               function = "scif_clk";
+       };
+
+       i2c0_pins: i2c0 {
+               groups = "i2c0";
+               function = "i2c0";
+       };
+
+       sdhi2_pins: sd2 {
+               groups = "sdhi2_data4", "sdhi2_ctrl";
+               function = "sdhi2";
+               power-source = <1800>;
+       };
+
+       sdhi3_pins: sd3 {
+               groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+               function = "sdhi3";
+               power-source = <1800>;
+       };
+};
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};
+
+&scif2 {
+       pinctrl-0 = <&scif2_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&sdhi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdhi2_pins>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       non-removable;
+       cap-power-off-card;
+       pm-ignore-notify;
+       keep-power-in-suspend;
+       mmc-pwrseq = <&wlan_pwrseq>;
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       brcmf: bcrmf@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+               interrupt-parent = <&gpio1>;
+               interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "host-wake";
+       };
+};
+
+&sdhi3 {
+       pinctrl-0 = <&sdhi3_pins>;
+       pinctrl-1 = <&sdhi3_pins>;
+       pinctrl-names = "default", "state_uhs";
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       bus-width = <8>;
+       mmc-hs200-1_8v;
+       non-removable;
+       fixed-emmc-driver-type = <1>;
+       status = "okay";
+};
+
+&usb_extal_clk {
+       clock-frequency = <50000000>;
+};
+
+&usb3s0_clk {
+       clock-frequency = <100000000>;
+};
+
+&vspb {
+       status = "okay";
+};
+
+&vspi0 {
+       status = "okay";
+};
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
new file mode 100644 (file)
index 0000000..a0c0a7f
--- /dev/null
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&cpg {
+       u-boot,dm-pre-reloc;
+};
+
+&extal_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&prr {
+       u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdhi0 {
+       /delete-property/ cd-gpios;
+};
+
+&sdhi2 {
+       status = "disabled";
+};
diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
new file mode 100644 (file)
index 0000000..e7ed5d4
--- /dev/null
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020, Compass Electronics Group, LLC
+ */
+
+/dts-v1/;
+
+#include "r8a774a1.dtsi"
+#include "beacon-renesom-som.dtsi"
+#include "beacon-renesom-baseboard.dtsi"
+
+/ {
+       model = "Beacon Embedded Works RZ/G2M Development Kit";
+       compatible =    "beacon,beacon-rzg2m", "renesas,r8a774a1";
+};
index bfd513a3616cc42f50228acb6e34a5d554312e24..07f607dd9d1ab544be74d177ea88c6ddf6cf9e0b 100644 (file)
@@ -46,6 +46,11 @@ choice
        prompt "Renesas ARM64 SoCs board select"
        optional
 
+config TARGET_BEACON_RZG2M
+       bool "Beacon EmbeddedWorks RZ/G2M Dev Kit"
+       select R8A774A1
+       select PINCTRL_PFC_R8A774A1
+
 config TARGET_CONDOR
        bool "Condor board"
        imply R8A77980
@@ -103,6 +108,7 @@ source "board/renesas/eagle/Kconfig"
 source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
+source "board/beacon/beacon-rzg2m/Kconfig"
 
 config MULTI_DTB_FIT_UNCOMPRESS_SZ
        default 0x80000 if TARGET_SALVATOR_X
diff --git a/board/beacon/beacon-rzg2m/Kconfig b/board/beacon/beacon-rzg2m/Kconfig
new file mode 100644 (file)
index 0000000..c03857c
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_BEACON_RZG2M
+
+config SYS_SOC
+       default "rmobile"
+
+config SYS_BOARD
+       default "beacon-rzg2m"
+
+config SYS_VENDOR
+       default "beacon"
+
+config SYS_CONFIG_NAME
+       default "beacon-rzg2m"
+
+endif
diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS
new file mode 100644 (file)
index 0000000..3383a68
--- /dev/null
@@ -0,0 +1,6 @@
+BEACON_RZG2M BOARD
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/beacon/beacon-rzg2m/
+F:     include/configs/beacon-rzg2m.h
+F:     configs/r8a774a1_beacon_defconfig
diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile
new file mode 100644 (file)
index 0000000..439f319
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# board/renesas/hihope-rzg2m/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := beacon-rzg2m.o
diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c
new file mode 100644 (file)
index 0000000..86a24dd
--- /dev/null
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/rcar-mstp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/* Kconfig forces this on, so just return 0 */
+int board_early_init_f(void)
+{
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       if (fdtdec_setup_mem_size_base() != 0)
+               return -EINVAL;
+
+       return 0;
+}
+
+int dram_init_banksize(void)
+{
+       fdtdec_setup_memory_banksize();
+
+       return 0;
+}
+
+#define RST_BASE       0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CODE       0xA5A5000F
+
+void reset_cpu(ulong addr)
+{
+       writel(RST_CODE, RST_CA57RESCNT);
+}
diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig
new file mode 100644 (file)
index 0000000..b62d670
--- /dev/null
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_BEACON_RZG2M=y
+# CONFIG_SPL is not set
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="r8a774a1-beacon-rzg2m-kit.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h
new file mode 100644 (file)
index 0000000..0e48fbd
--- /dev/null
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __BEACON_RZG2M_H
+#define __BEACON_RZG2M_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* #define CONFIG_ENV_OFFSET           (-CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_MMC_ENV_DEV         1
+#define CONFIG_SYS_MMC_ENV_PART                2
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "usb_pgood_delay=2000\0"        \
+       "script=boot.scr\0" \
+       "image=Image\0" \
+       "console=ttySC0,115200\0" \
+       "fdt_addr=0x48000000\0" \
+       "loadaddr=0x48080000\0" \
+       "boot_fdt=try\0" \
+       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       "initrd_addr=0x43800000\0"              \
+       "mmcdev=0\0" \
+       "mmcpart=1\0" \
+       "mmcrootpart=2\0" \
+       "finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
+       "mmcautodetect=yes\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+       " root=PARTUUID=${uuid} rootwait rw ${optargs}\0" \
+       "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run finduuid; run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "booti ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "echo WARN: Cannot load the DT; " \
+                       "fi; " \
+               "else " \
+                       "echo wait for boot; " \
+               "fi;\0" \
+       "netargs=setenv bootargs ${jh_clk} console=${console} " \
+               "root=/dev/nfs " \
+               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+       "netboot=echo Booting from net ...; " \
+               "run netargs;  " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${loadaddr} ${image}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "booti ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "echo WARN: Cannot load the DT; " \
+                       "fi; " \
+               "else " \
+                       "booti; " \
+               "fi;\0"
+
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND \
+       "mmc dev ${mmcdev}; if mmc rescan; then " \
+          "if run loadbootscript; then " \
+                  "run bootscript; " \
+          "else " \
+                  "if run loadimage; then " \
+                          "run mmcboot; " \
+                  "else run netboot; " \
+                  "fi; " \
+          "fi; " \
+       "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+#endif /* __BEACON_RZG2M_H */