imx8ulp: clock: Reset DDR controller before clock enable

The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index e599e6c4c67a7705031b15088dcdb8c16ca676df..f54fc25763c3e36493d77656d2924c5ab4116f78 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -97,6 +97,9 @@ void ddrphy_pll_lock(void)
 
 void init_clk_ddr(void)
 {
+       /* disable the ddr pcc */
+       writel(0xc0000000, PCC5_LPDDR4_ADDR);
+
        /* enable pll4 and ddrclk*/
        cgc2_pll4_init();
        cgc2_ddrclk_config(1, 1);