Move ROCKCHIP_STIMER_BASE to Kconfig.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.
+config ROCKCHIP_STIMER
+ bool "Rockchip STIMER support"
+ default y
+ help
+ Enable Rockchip STIMER support.
+
+config ROCKCHIP_STIMER_BASE
+ hex
+ depends on ROCKCHIP_STIMER
+
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
+config ROCKCHIP_STIMER_BASE
+ default 0xff220020
+
config SYS_SOC
default "px30"
config ROCKCHIP_BOOT_MODE_REG
default 0x200081c8
+config ROCKCHIP_STIMER_BASE
+ default 0x200440a0
+
config SYS_SOC
default "rk3036"
config ROCKCHIP_BOOT_MODE_REG
default 0x100a0038
+config ROCKCHIP_STIMER_BASE
+ default 0x200440a0
+
config SYS_SOC
default "rk3128"
config ROCKCHIP_BOOT_MODE_REG
default 0x110005c8
+config ROCKCHIP_STIMER_BASE
+ default 0x110d0020
+
config SYS_SOC
default "rk322x"
config ROCKCHIP_BOOT_MODE_REG
default 0xff730094
+config ROCKCHIP_STIMER_BASE
+ default 0xff810020
+
config SYS_SOC
default "rk3288"
bool "Firefly roc-rk3308-cc"
select BOARD_LATE_INIT
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff000500
+
+config ROCKCHIP_STIMER_BASE
+ default 0xff1b00a0
+
config SYS_SOC
default "rk3308"
config SPL_SERIAL
default y
-config ROCKCHIP_BOOT_MODE_REG
- default 0xff000500
-
-
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"
config ROCKCHIP_BOOT_MODE_REG
default 0xff1005c8
+config ROCKCHIP_STIMER_BASE
+ default 0xff1d0020
+
config SYS_SOC
default "rk3328"
config ROCKCHIP_BOOT_MODE_REG
default 0xff738200
+config ROCKCHIP_STIMER_BASE
+ default 0xff830020
+
config SYS_SOC
default "rk3368"
config ROCKCHIP_BOOT_MODE_REG
default 0xff320300
+config ROCKCHIP_STIMER_BASE
+ default 0xff8680a0
+
config SYS_SOC
default "rk3399"
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
+config ROCKCHIP_STIMER_BASE
+ default 0xfdd1c020
+
config SYS_SOC
default "rk3568"
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_SPL_TEXT_BASE=0x10080800
CONFIG_ROCKCHIP_RK3188=y
+# CONFIG_ROCKCHIP_STIMER is not set
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEBUG_UART_BASE=0x20064000
#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
#define COUNTER_FREQUENCY 24000000
/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
-#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
#define CONFIG_IRAM_BASE 0xfff80000
#define CONFIG_SYS_INIT_SP_ADDR 0x00800000
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_IRAM_BASE 0xff090000
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_CBSIZE 1024
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
#define COUNTER_FREQUENCY 24000000
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_CBSIZE 1024
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0
#define CONFIG_IRAM_BASE 0xff8c0000
#define CONFIG_SYS_CBSIZE 1024
#define COUNTER_FREQUENCY 24000000
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
#define CONFIG_IRAM_BASE 0xfdcc0000