ls102xa: etsec: Add etsec support for LS102xA

This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f03381da8928a41882128d8680f2a7aaa2f..79d656133adb4d50a7a28dfb529f81121db708ac 100644 (file)
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+       setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 
        do {
                uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+       setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device. The return value

diff --git a/include/tsec.h b/include/tsec.h
index 20547153a1937cacaeb194aa3a64c24ae7f46584..1119d2cb60be8c4dd3943f383093e9b595f34abb 100644 (file)
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <fsl_mdio.h>
 
+#ifdef CONFIG_LS102XA
+#define TSEC_SIZE              0x40000
+#define TSEC_MDIO_OFFSET       0x40000
+#else
 #define TSEC_SIZE              0x01000
 #define TSEC_MDIO_OFFSET       0x01000
+#endif
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 
@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS  0x000000c3
 #define DMACTRL_GRS            0x00000010
 #define DMACTRL_GTS            0x00000008
+#define DMACTRL_LE             0x00008000
 
 #define TSTAT_CLEAR_THALT      0x80000000
 #define RSTAT_CLEAR_RHALT      0x00800000