__weak int dram_init(void)
{
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#include <asm/addrspace.h>
#include <mach/ddr.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ddr_tap_tuning();
return get_ram_size((void *)KSEG1, SZ_256M);
}
/* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ddr2_pmd_ungate();
ddr2_phy_init();
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram(0);
+ initdram();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
#endif
}
#else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = 0;
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
unsigned long val;
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong speed;
ulong sdtr1;
* so this should be extended for other future boards
* using this routine!
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
int i;
int tr1_bank1;
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram(0);
+ initdram();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
return 0;
}
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
int size, i;
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
uint svr, pvr;
return;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
int i;
u32 val;
}
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
return spd_sdram();
}
}
/* -------------------------------------------------------------------------
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ initdram() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return spd_sdram();
}
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
}
/*
- * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * initdram() reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return spd_sdram();
}
*tr1_value = (first_good + last_bad) / 2;
}
-phys_size_t initdram(int board)
+phys_size_t initdram(void)
{
register uint reg;
int tr1_bank1, tr1_bank2;
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
mem_conf_t *mem_conf;
- mem_conf = get_mem_config(board_type);
+ mem_conf = get_mem_config(gd->board_type);
/* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
return 0;
};
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
return fixed_sdram(NULL, NULL, 0);
}
#include <asm/mipsregs.h>
#include <asm/io.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
}
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t size;
int n;
void ddr_enable_ecc(unsigned int dram_size);
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
popts->cpo_sample = 0x3e;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
puts("\n\n");
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
nand_boot();
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
return 0;
}
#endif
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
popts->cpo_sample = 0x70;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
popts->cpo_sample = 0x70;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
return 0;
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
}
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
}
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
};
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
unsigned long junk = 0xa5a59696;
/*
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize = 0;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
/*
* Check to see if the SDRAM has already been initialized
return 0;
};
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
out_be16(&sdp->sdram_sdtr, 0xf539);
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
return 0;
}
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
u32 dramsize, i, dramclk;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize;
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
return 0;
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
return(ismicron);
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 msize = 0;
/*
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
- initdram(0);
+ initdram();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
return msize;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
- initdram(0);
+ initdram();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
}
#endif /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize;
int fixed_sdram(void);
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
int fixed_sdram(void);
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
phys_size_t msize = 0;
};
#endif /* CONFIG_PCI */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#endif
int fixed_sdram(void);
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#endif
int fixed_sdram(void);
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
}
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = 0;
return 0;
}
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = 0;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("\nTertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = 0;
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
}
#endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
puts("\n\n");
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x54;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x63;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
i2c_init_all();
- gd->ram_size = initdram(0);
+ gd->ram_size = initdram();
mmc_boot();
}
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return 1;
}
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return 1;
}
#include <config.h>
#include <asm/leon.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return 1;
}
#include <common.h>
#include <asm/leon.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return 1;
}
#include <common.h>
#include <asm/leon.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return 1;
}
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
return msize;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
fsl_lbc_t *lbc = &im->im_lbc;
/* EMPTY, optional, we don't do it */
};
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
}
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
#include "boston-regs.h"
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
}
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return CONFIG_SYS_MEM_SIZE;
}
#include <common.h>
/* initialize the DDR Controller and PHY */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#endif /* CONFIG_SYS_SDRAM_LIST */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
memctl8260_t *memctl = &immap->im_memctl;
return msize;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = 0;
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
* SDRAM is already configured by the bootstrap code, only return the
* auto-detected size here
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_MBYTES_SDRAM << 20);
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ initdram() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
unsigned long bank_reg[4], tmp, bank_size;
/*
* Get RAM size.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
unsigned char board_rev;
unsigned long reg;
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ initdram() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
unsigned long bank_reg[4], tmp, bank_size;
int i, ds;
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#include <asm/mipsregs.h>
#include <asm/io.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
},
};
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
int i;
u32 msize = 0;
* is something else than 0x00000000.
*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
#include <asm/io.h>
#include <netdev.h>
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
return 0;
}
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
long dram_size = 0;
asm volatile ("nop");
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
u32 dramsize, RC;
* is something else than 0x00000000.
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/**************************************************************************
* DRAM initalization and size detection
*/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
long bank_size;
long size;
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9, size10;
long int size_b0 = 0;
long int size_b1 = 0;
+ int board_type = gd->board_type;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
#endif /* !CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size;
return msize;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return spd_sdram();
}
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
phys_size_t dram_size = fsl_ddr_sdram();
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
return 0;
}
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
static int init_func_ram(void)
{
-#ifdef CONFIG_BOARD_TYPES
- int board_type = gd->board_type;
-#else
- int board_type = 0; /* use dummy arg */
-#endif
-
- gd->ram_size = initdram(board_type);
+ gd->ram_size = initdram();
if (gd->ram_size > 0)
return 0;
} gd_t;
#endif
+#ifdef CONFIG_BOARD_TYPES
+#define gd_board_type() gd->board_type
+#else
+#define gd_board_type() 0
+#endif
+
/*
* Global Data Flags - the top 16 bits are reserved for arch-specific flags
*/
int cpu_init(void);
/* */
-phys_size_t initdram (int);
+phys_size_t initdram(void);
#include <display_options.h>