Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
/*
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
#endif
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
} else {
puts("CPU: ");
val |= 0x70000000;
mtspr(DBCR0,val);
#else
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Call board-specific preparation for reset */
board_reset_prepare();
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;
unsigned int i;
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
- (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
void fsl_erratum_a007212_workaround(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
#ifdef CONFIG_ARCH_MPC8548
- ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
/*
{
int i = 0;
u32 cluster, svr = get_svr();
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
/* only the L2 of first cluster should be enabled as expected on T4080,
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_L2_CACHE
- ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
{
struct ccsr_usb_phy __iomem *usb_phy1 =
- (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
fsl_erratum_a006261_workaround(usb_phy1);
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
{
struct ccsr_usb_phy __iomem *usb_phy2 =
- (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
fsl_erratum_a006261_workaround(usb_phy2);
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
struct ccsr_usb_phy __iomem *usb_phy =
- (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
setbits_be32(&usb_phy->pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
fsl_sata_reg_t *reg;
/* first SATA controller */
- reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+ reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
/* second SATA controller */
- reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+ reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
}
#endif
{
u32 mas0, mas1, mas2, mas3, mas7;
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#ifdef CONFIG_A003399_NOR_WORKAROUND
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
u32 *dst, *src;
void (*setup_ifc_sram)(void);
int i;
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
- volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
u32 ver = SVR_SOC_VER(get_svr());
#if defined(CONFIG_ARCH_P4080)
static void fdt_fixup_usb(void *fdt)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
int off;
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
int nodeoff;
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_ARCH_T2080)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 cfg;
int lane;
int serdes_lane_enabled(int lane)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int is_serdes_configured(enum srds_prtcl device)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
u32 prtcl;
const ccsr_gur_t *gur;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
if (unlikely(device == NONE))
return;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
#ifdef CONFIG_ARCH_P5040
void interrupt_init_cpu(unsigned *decrementer_count)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
#ifdef CONFIG_POST
/*
int cpu_reset(u32 nr)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
/* the dummy read works around an errata on early 85xx MP PICs */
(void)in_be32(&pic->pir);
#ifdef CONFIG_FSL_CORENET
int cpu_disable(u32 nr)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->coredisrl, 1 << nr);
}
int is_core_disabled(int nr) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 coredisrl = in_be32(&gur->coredisrl);
return (coredisrl & (1 << nr));
#else
int cpu_disable(u32 nr)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
switch (nr) {
case 0:
}
int is_core_disabled(int nr) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
switch (nr) {
u32 mask = cpu_mask();
struct law_entry e;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
- pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);
cpu_up_mask = 1 << whoami;
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)&__spin_table;
volatile u32 bpcr;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 devdisr;
int timeout = 10;
void fsl_serdes_init(void)
{
- void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
+ void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
u32 srds1_io_sel, srds2_io_sel;
u32 tmp;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
&(gur->qe_par_io);
void get_sys_info(sys_info_t *sys_info)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
{
sys_info_t sys_info;
#ifdef CONFIG_ARCH_MPC8544
- volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
/* Definitions from C header file asm/immap_85xx.h */
-#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
#define MPC85xx_L2CTL 0x000
#define MPC85xx_L2CTL_L2E 0x80000000
.org 0x80 /* Start of configuration */
.Lconf_pair_start:
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
.long CONFIG_SYS_INIT_L2_ADDR
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
void ExtIntException(struct pt_regs *regs)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
uint vect;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
static inline u32 init_type(u32 cluster, int init_id)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = in_be32(&gur->tp_ityp[idx]);
u32 compute_ppc_cpumask(void)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
u32 compute_dsp_cpumask(void)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = CONFIG_DSP_CLUSTER_START, count = 0;
u32 cluster, type, dsp_mask = 0;
int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int count = 0, i = CONFIG_DSP_CLUSTER_START;
u32 cluster;
int fsl_qoriq_core_to_cluster(unsigned int core)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
*/
__weak u32 cpu_mask(void)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */
#ifdef CONFIG_HETROGENOUS_CLUSTERS
__weak u32 cpu_dsp_mask(void)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* check RCW to get which port is used for boot */
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 bootloc = in_be32(&gur->rcwsr[6]);
/*
* in SRIO or PCIE boot we need to set specail LAWs for
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
#endif
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+ #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+ #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
#define SET_SRIO_LIODN_1(port, idA) \
{ .id = { idA }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_2(port, idA, idB) \
{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
.reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_BASE(port, id_a) \
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
SET_LIODN_ENTRY_1(compat, liodn, \
- offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+ offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
compatoff)
#define SET_USB_LIODN(usbNum, compat, liodn) \
SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
- CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+ CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
#define SET_SATA_LIODN(sataNum, liodn) \
SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
- CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+ CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
#define SET_PCI_LIODN(compat, pciNum, liodn) \
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
- CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+ CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
SET_LIODN_ENTRY_1(compat, liodn,\
- offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
- CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+ offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, compat, liodn) \
SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
- CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+ CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
#define SET_SDHC_LIODN(sdhcNum, liodn) \
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
- CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+ CFG_SYS_MPC85xx_ESDHC_OFFSET)
#define SET_QE_LIODN(liodn) \
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
- CONFIG_SYS_MPC85xx_QE_OFFSET)
+ CFG_SYS_MPC85xx_QE_OFFSET)
#define SET_TDM_LIODN(liodn) \
SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
- CONFIG_SYS_MPC85xx_TDM_OFFSET)
+ CFG_SYS_MPC85xx_TDM_OFFSET)
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
};
};
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
+#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_FSL_DDR_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
+#define CFG_SYS_MPC83xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
+#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
+#define CFG_SYS_MPC83xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
-#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
+#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
-#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
-#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
-#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
-#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
-#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
+#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
+#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
+#define CFG_SYS_MPC85xx_DMA_OFFSET CFG_SYS_MPC85xx_DMA1_OFFSET
+#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x110000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
+#define CFG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CFG_SYS_MPC85xx_IFC_OFFSET 0x124000
+#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
+#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
!defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
#else
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
#endif
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
+#define CFG_SYS_MPC85xx_USB1_OFFSET 0x210000
+#define CFG_SYS_MPC85xx_USB2_OFFSET 0x211000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
-#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
-#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
+#define CFG_SYS_MPC85xx_LBC_OFFSET 0x5000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
+#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CFG_SYS_MPC85xx_PCI1_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCI2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
#if defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
#endif
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
-#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
+#define CFG_SYS_MPC85xx_GPIO_OFFSET 0xF000
+#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x18000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CFG_SYS_MPC85xx_IFC_OFFSET 0x1e000
+#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CFG_SYS_MPC85xx_DMA_OFFSET 0x21000
+#define CFG_SYS_MPC85xx_USB1_OFFSET 0x22000
+#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
#elif defined(CONFIG_TSECV2_1)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
#endif
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
+#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
+#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
+#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_MPC85xx_GUTS_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_MPC85xx_ECM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_FSL_DDR_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_FSL_DDR2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_FSL_DDR3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_IFC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
+#define CFG_SYS_MPC85xx_ESPI_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CFG_SYS_MPC85xx_GPIO_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
+#define CFG_SYS_MPC85xx_SATA1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
+#define CFG_SYS_MPC85xx_SATA2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
+#define CFG_SYS_MPC85xx_L2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
+#define CFG_SYS_MPC85xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
+#define CFG_SYS_MPC85xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_PIC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
#define CONFIG_SYS_PCI2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
#define CONFIG_SYS_PCIE1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
#define CONFIG_SYS_PCIE2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_PCIE3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
#define CONFIG_SYS_PCIE4_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
#define CONFIG_SYS_SFP_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
-#define CONFIG_SYS_MPC85xx_SCFG \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
-#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+#define CFG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
+#define CFG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
/* The supplement configuration unit register */
struct ccsr_scfg {
u32 dpslpcr; /* 0x000 Deep Sleep Control register */
static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of "dir" and "val" */
dir &= mask;
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */
return in_be32(&gpio->gpdat) & mask;
#endif
#if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#else
#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
#endif
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
u32 flash_addr, addr;
bool is_warm_boot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
{
u64 *src, *dst;
int i;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
{
u32 start_addr;
void (*kernel_resume)(void);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
if (!is_warm_boot())
return 0;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
u8 vid;
u32 fusesr;
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
int board_early_init_f(void)
{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Clock configuration to access CPLD using IFC(GPCM) */
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
int config_board_mux(int ctrl_type)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
#if CONFIG_IS_ENABLED(DM_I2C)
int misc_init_r(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
console_init_f();
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
void board_gpio_init(void)
{
#ifdef CONFIG_QE
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
/* Enable VSC7385 switch */
setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
#else
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/*
* GPIO10 DDR Reset, open drain
int board_early_init_f(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
#ifndef SDHC_WP_IS_GPIO
int checkboard(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, invert, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_TSEC1
static void fix_max6370_watchdog(void *blob)
{
int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 gpioval = in_be32(&pgpio->gpdat);
/*
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
int board_early_init_f(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
setbits_be32(&gur->ddrclkdr, 0x000f000f);
void board_config_lanes_mux(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD */
int board_mmc_getwp(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL;
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 reg = CPLD_READ(misc_ctl_status);
int board_mmc_getcd(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD/MMC */
int board_mmc_getwp(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL;
static u32 t1023rdb_ctrl(u32 ctrl_type)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 val;
u8 tmp;
int bus_num = I2C_PCA6408_BUS_NUM;
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+ GPIO3_OFFSET);
val = in_be32(&pgpio->gpdat);
val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+ GPIO3_OFFSET);
val = in_be32(&pgpio->gpdat);
val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
- CONFIG_SYS_MPC85xx_SCFG;
+ CFG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
(0x80000000));
u32 porsr1, pinctl;
u32 svr = get_svr();
#endif
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
if (IS_SVR_REV(svr, 1, 0)) {
int misc_init_r(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
const char *phyconn;
int off;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
*/
static void initialize_lane_to_slot(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
u32 srds_s1;
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
int brd_mux_lane_to_slot(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
bool cpuwd_flag = false;
/* board specific IFC configuration: increased bus turnaround time */
int misc_init_r(void)
{
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
- ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
+ ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* check SERDES bank 0 reference clock */
u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
char buf[64];
int f;
int i = env_get_f("serial#", buf, sizeof(buf));
void local_bus_init (void)
{
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
uint lbc_mhz;
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* set and reset the GPIO pin 2 which will reset the W83782G chip */
out_8((unsigned char*)&gur->gpoutdr, 0x3F );
unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
*/
unsigned long get_board_ddr_clk(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
uint get_board_derivative(void)
{
#if defined(CONFIG_MPC85xx)
- volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#elif defined(CONFIG_MPC86xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
uint svr;
#endif
int timeout;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
int timeout_save;
- volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR;
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
#if defined(CONFIG_MPC83xx)
-dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
+dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
#elif defined(CONFIG_MPC85xx)
-ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
#else
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
u32 serdes2_prtcl;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
return port_to_devdisr[port] & devdisr;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
/* handle RGMII first */
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
#ifdef CONFIG_ARCH_LS1021A
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
#ifdef CONFIG_ARCH_LS1021A
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
const u32 *code;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_PPC
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#else
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
#endif
struct uec_priv *uec = (struct uec_priv *)dev->priv;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII management signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (struct uec_priv *)dev->priv;
if (!fsl)
return NULL;
- fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR);
fsl->mode = mode;
fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
fsl->speed_hz = max_hz;
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
#endif
/*
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
#endif
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
#elif defined (CONFIG_MPC85xx)
#include <asm/immap_85xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
#endif
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