ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()

Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index cad8d4649c1360b44fd0d1495b2d2821604c15df..5c2a2ab0f28d785e0b8e71756c80980336f005a5 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -111,22 +111,10 @@ void enable_basic_clocks(void)
                &cmper->emifclkctrl,
                &cmper->otfaemifclkctrl,
                &cmper->qspiclkctrl,
-               &cmper->usb0clkctrl,
-               &cmper->usbphyocp2scp0clkctrl,
-               &cmper->usb1clkctrl,
-               &cmper->usbphyocp2scp1clkctrl,
                &cmper->spi0clkctrl,
                0
        };
 
-       setbits_le32(&cmper->usb0clkctrl,
-                    USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
-       setbits_le32(&cmwkup->usbphy0clkctrl,
-                    USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
-       setbits_le32(&cmper->usb1clkctrl,
-                    USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
-       setbits_le32(&cmwkup->usbphy1clkctrl,
-                    USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
        /* Select the Master osc clk as Timer2 clock source */

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index bec6539ef52ec596bfc149d8f94a06c236716084..7f8c0a423bad59305ecaa2ce4e4ae8d5ee9c65de 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,13 +460,6 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio6_clkctrl,
                (*prcm)->cm_l4per_gpio7_clkctrl,
                (*prcm)->cm_l4per_gpio8_clkctrl,
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-               (*prcm)->cm_l3init_ocp2scp1_clkctrl,
-               (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-               (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-#endif
-#endif
                0
        };
 
@@ -498,29 +491,6 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-       /* Enable 960 MHz clock for dwc3 */
-       setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-                    OPTFCLKEN_REFCLK960M);
-
-       /* Enable 32 KHz clock for dwc3 */
-       setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
-                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-       /* Enable 960 MHz clock for dwc3 */
-       setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-                    OPTFCLKEN_REFCLK960M);
-
-       /* Enable 32 KHz clock for dwc3 */
-       setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
-                    USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-       /* Enable 60 MHz clock for USB2PHY2 */
-       setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
-                    L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
-#endif
-#endif
-
        /* Set the correct clock dividers for mmc */
        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_DIV_MASK);