sh: Add register definition of PFC for SH7734

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h
index e3becc971e9230ca54f4f8c25165a132772a70af..0f84b4f57ca2fb36d77ae23395ce222c78e783f9 100644 (file)
--- a/arch/sh/include/asm/cpu_sh7734.h
+++ b/arch/sh/include/asm/cpu_sh7734.h
@@ -40,4 +40,31 @@
 #define TCNT0  0xFFD8000C
 #define TCR0   0xFFD80010
 
+/* PFC */
+#define PMMR    (0xFFFC0000)
+#define MODESEL0    (0xFFFC004C)
+#define MODESEL2    (MODESEL0 + 0x4)
+#define MODESEL2_INIT   (0x00003000)
+
+#define IPSR0  (0xFFFC001C)
+#define IPSR1  (IPSR0 + 0x4)
+#define IPSR2  (IPSR0 + 0x8)
+#define IPSR3  (IPSR0 + 0xC)
+#define IPSR4  (IPSR0 + 0x10)
+#define IPSR5  (IPSR0 + 0x14)
+#define IPSR6  (IPSR0 + 0x18)
+#define IPSR7  (IPSR0 + 0x1C)
+#define IPSR8  (IPSR0 + 0x20)
+#define IPSR9  (IPSR0 + 0x24)
+#define IPSR10 (IPSR0 + 0x28)
+#define IPSR11 (IPSR0 + 0x2C)
+
+#define GPSR0  (0xFFFC0004)
+#define GPSR1  (GPSR0 + 0x4)
+#define GPSR2  (GPSR0 + 0x8)
+#define GPSR3  (GPSR0 + 0xC)
+#define GPSR4  (GPSR0 + 0x10)
+#define GPSR5  (GPSR0 + 0x14)
+
+
 #endif /* _ASM_CPU_SH7734_H_ */