arm: mach: exynos: Remove duplicate newlines

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h
index 4f56160ee50a2d7f0bf02121821857181ae953e9..a3fc7d9fbebb3984010af4eefe90304e18c2ca5b 100644 (file)
--- a/arch/arm/mach-exynos/common_setup.h
+++ b/arch/arm/mach-exynos/common_setup.h
@@ -61,7 +61,6 @@ enum l2_cache_params {
        CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
 };
 
-
 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
 /*
  * Configure L2CTLR to get timings that keep us from hanging/crashing.

diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h
index 23c9011fbc63a0bb60b49c169019673528eb7190..1a287a4ef6a390314b94f485e3b286e53145e6b5 100644 (file)
--- a/arch/arm/mach-exynos/exynos4_setup.h
+++ b/arch/arm/mach-exynos/exynos4_setup.h
@@ -284,7 +284,6 @@
 #define MFC_0_SEL              MFC_SEL_MPLL
 #define CLK_SRC_MFC_VAL                ((MFC_SEL << 8) | (MFC_0_SEL))
 
-
 /* CLK_DIV_MFC */
 #define MFC_RATIO              3
 #define CLK_DIV_MFC_VAL                (MFC_RATIO)
@@ -498,7 +497,6 @@ struct mem_timings {
                                | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
                                | NUM_CHIP_2 | BL_8)
 
-
 #define CHIP_BANK_8            (0x3 << 0)
 #define CHIP_ROW_14            (0x2 << 4)
 #define CHIP_COL_10            (0x3 << 8)

diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h
index 4e508edba0c6b49d7ea0fe580f51b07c2c3175e8..6fa80221c8d6cbbabf01fb5250bce284d4d8b8e2 100644 (file)
--- a/arch/arm/mach-exynos/exynos5_setup.h
+++ b/arch/arm/mach-exynos/exynos5_setup.h
@@ -685,7 +685,6 @@
 #define PWM_RATIO              8
 #define CLK_DIV_PERIC3_VAL     (PWM_RATIO << 0)
 
-
 /* CLK_DIV_PERIC4 */
 #define CLK_DIV_PERIC4_VAL     NOT_AVAILABLE
 
@@ -710,7 +709,6 @@
 /* MPLL_CON1 */
 #define MPLL_CON1_VAL   (0x0020F300)
 
-
 /* CPLL_CON1 */
 #define CPLL_CON1_VAL  0x0020f300
 
@@ -720,7 +718,6 @@
 /* GPLL_CON1 */
 #define GPLL_CON1_VAL  (NOT_AVAILABLE)
 
-
 /* EPLL_CON1, CON2 */
 #define EPLL_CON1_VAL  0x00000000
 #define EPLL_CON2_VAL  0x00000080
@@ -750,7 +747,6 @@
 #define CLK_DIV_ISP0_VAL       0x13131300
 #define CLK_DIV_ISP1_VAL       0xbb110202
 
-
 /* CLK_FSYS */
 #define CLK_SRC_FSYS0_VAL              0x33033300
 #define CLK_DIV_FSYS0_VAL             0x0

diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index dab148e3320e545c7c8f3d88a7f95a0437cba4de..cf4580be189abe60dff0625921cd5b4a3a8371ec 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -190,7 +190,6 @@
 #define EXYNOS5420_MODEM_BASE          DEVICE_NOT_AVAILABLE
 #define EXYNOS5420_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
 
-
 #ifndef __ASSEMBLY__
 #include <asm/io.h>
 /* CPU detection macros */

diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h
index 3226eb95f0151874ecfbe855ddfd3527829f71df..a7f7667afd6d5b1b62493dfafcb0989ceb92b9cd 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/dp_info.h
+++ b/arch/arm/mach-exynos/include/mach/dp_info.h
@@ -183,7 +183,6 @@ enum {
        VIDEO_TIMING_FROM_REGISTER
 };
 
-
 struct exynos_dp_platform_data {
        struct exynos_dp_priv *edp_dev_info;
 };

diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h
index 757e1586bde4deb0dd0def4ae5855b0d29baa69a..32534116cf881ac472d5d30630e3bfe87f166389 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/power.h
+++ b/arch/arm/mach-exynos/include/mach/power.h
@@ -1752,7 +1752,6 @@ void set_xclkout(void);
  */
 uint32_t get_reset_status(void);
 
-
 /* Read the resume function and call it */
 void power_exit_wakeup(void);
 

diff --git a/arch/arm/mach-exynos/include/mach/sound.h b/arch/arm/mach-exynos/include/mach/sound.h
index 1a40e35f0b582dd1f9abad26f5709bc6a297f6a3..9672e977f0760c2f64029accff243ba1d57147a1 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/sound.h
+++ b/arch/arm/mach-exynos/include/mach/sound.h
@@ -4,7 +4,6 @@
  * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  */
 
-
 #ifndef __SOUND_ARCH_H__
 #define __SOUND_ARCH_H__
 

diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c
index 4061dd4aafaea117b6289cc38fc3bacdb5fe3dea..07d19fd17ba455e09a83ecc20ce108e8166ae485 100644 (file)
--- a/arch/arm/mach-exynos/pinmux.c
+++ b/arch/arm/mach-exynos/pinmux.c
@@ -391,7 +391,6 @@ static void exynos5420_i2s_config(int peripheral)
        }
 }
 
-
 void exynos5_spi_config(int peripheral)
 {
        int cfg = 0, pin = 0, i;

diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index 599d3ccff60326fe5dd1afb6680cb35393a4738b..1b61da6dc1a32b5ef38f5ff9136af6a593e9cd6a 100644 (file)
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -20,7 +20,6 @@ static void exynos4_mipi_phy_control(unsigned int dev_index,
        else
                addr = (unsigned int)&pmu->mipi_phy1_control;
 
-
        cfg = readl(addr);
        if (enable)
                cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
@@ -174,7 +173,6 @@ void set_ps_hold_ctrl(void)
                exynos5_set_ps_hold_ctrl();
 }
 
-
 static void exynos5_set_xclkout(void)
 {
        struct exynos5_power *power =

diff --git a/arch/arm/mach-s5pc1xx/include/mach/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h
index 78c905b866b9c086223bc03323783f95f8649688..4b1b711826847bb086af77e5e5650ff13e98b864 100644 (file)
--- a/arch/arm/mach-s5pc1xx/include/mach/cpu.h
+++ b/arch/arm/mach-s5pc1xx/include/mach/cpu.h
@@ -45,7 +45,6 @@
 #define S5PC110_PHY_BASE       0xEC100000
 #define S5PC110_USB_PHY_CONTROL 0xE010E80C
 
-
 #ifndef __ASSEMBLY__
 #include <asm/io.h>
 /* CPU detection macros */