spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>

diff --git a/README b/README
index 211bad03d53bb986b5e7b6142538ae0cd026ee10..ca2d10f8ed804317aa7f4fa30c51e64448b58ac8 100644 (file)
--- a/README
+++ b/README
@@ -2677,6 +2677,9 @@ FIT uImage format:
                For ARM, enable an optional function to print more information
                about the running system.
 
+               CONFIG_SPL_INIT_MINIMAL
+               Arch init code should be built for a very small image
+
                CONFIG_SPL_LIBCOMMON_SUPPORT
                Support for common/libcommon.o in SPL binary
 

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index a7dbfa78599dc3ab5e5c33037aacfca176720322..4c2b1040d4613317b2365ddce77bdf23ffc21493 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(CPU).o
 
-START  = start.o resetvec.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+START = start.o resetvec.o
+
+ifdef MINIMAL
+
+COBJS-y        += cpu_init_early.o tlb.o spl_minimal.o
+
+else
+
 SOBJS-$(CONFIG_MP)     += release.o
 SOBJS  = $(SOBJS-y)
 
@@ -132,6 +147,8 @@ COBJS-y     += traps.o
 # Stub implementations of cache management functions for USB
 COBJS-y += cache.o
 
+endif # not minimal
+
 COBJS  = $(COBJS-y)
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 577d6874ba6ccf41608b8570108509cd8b7d4104..bb0dc1a653e193fb1f141e13ede0980f0c075198 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -44,6 +44,15 @@
 #undef MSR_KERNEL
 #define MSR_KERNEL ( MSR_ME )  /* Machine Check */
 
+#if defined(CONFIG_NAND_SPL) || \
+       (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#define NOR_BOOT
+#endif
+
 /*
  * Set up GOT: Global Offset Table
  *
@@ -53,7 +62,7 @@
        GOT_ENTRY(_GOT2_TABLE_)
        GOT_ENTRY(_FIXUP_TABLE_)
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        GOT_ENTRY(_start)
        GOT_ENTRY(_start_of_vectors)
        GOT_ENTRY(_end_of_vectors)
@@ -282,11 +291,8 @@ l2_disabled:
        isync
        .endm
 
-/*
- * Ne need to setup interrupt vector for NAND SPL
- * because NAND SPL never compiles it.
- */
-#if !defined(CONFIG_NAND_SPL)
+/* Interrupt vectors do not fit in minimal SPL. */
+#if !defined(MINIMAL_SPL)
        /* Setup interrupt vectors */
        lis     r1,CONFIG_SYS_MONITOR_BASE@h
        mtspr   IVPR,r1
@@ -518,7 +524,7 @@ nexti:      mflr    r1              /* R1 = our PC */
  * in AS1.
  */
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
@@ -1032,7 +1038,7 @@ create_init_ram_area:
        lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
        ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
        /* create a temp mapping in AS=1 to the 4M boot window */
        create_tlb1_entry 15, \
                1, BOOKE_PAGESZ_4M, \
@@ -1107,7 +1113,8 @@ switch_as:
        bdnz    1b
 
        /* Jump out the last 4K page and continue to 'normal' start */
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+       /* We assume that we're already running at the address we're linked at */
        b       _start_cont
 #else
        /* Calculate absolute address in FLASH and jump there           */
@@ -1153,7 +1160,7 @@ _start_cont:
 
        /* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        . = EXC_OFF_SYS_RESET
        .globl  _start_of_vectors
 _start_of_vectors:
@@ -1597,7 +1604,7 @@ in32:
 in32r:
        lwbrx   r3,r0,r3
        blr
-#endif  /* !CONFIG_NAND_SPL */
+#endif  /* !MINIMAL_SPL */
 
 /*------------------------------------------------------------------------------*/
 
@@ -1794,7 +1801,7 @@ clear_bss:
        mr      r4,r10          /* Destination Address          */
        bl      board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        /*
         * Copy exception vector code to low memory
         *
@@ -1967,4 +1974,4 @@ setup_ivors:
 
 #include "fixed_ivor.S"
        blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */

diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 86344a7b4a0d2a86addea6e412a70aa47a005b66..3dc8e055b68ba905bdddb0fecc08478a82ca6ff8 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib8xxx.o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-$(CONFIG_FSL_LAW) += law.o
+
+else
+
 ifneq ($(CPU),mpc83xx)
 COBJS-y        += cpu.o
 endif
@@ -20,6 +34,8 @@ COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 COBJS-$(CONFIG_FSL_LAW) += law.o
 
+endif
+
 SRCS   := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 

diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 4a4163532a47bfb2c9b17a0fa082e3c19bd2b22e..20c5c3803bb7064bc07e825901d7b767a6926dbd 100644 (file)
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -38,8 +38,21 @@ endif
 
 LIB    = $(obj)lib$(ARCH).o
 
-SOBJS-y        += ppccache.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+COBJS-y += cache.o
+else
+
 SOBJS-y        += ppcstring.o
+
+SOBJS-y        += ppccache.o
 SOBJS-y        += ticks.o
 SOBJS-y        += reloc.o
 
@@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
 COBJS-y += memcpy_mpc5200.o
 endif
 
+endif # not minimal
+
 COBJS  += $(sort $(COBJS-y))
 
 SRCS   := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \