]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: imx8mq: Add USB clock init function
authorYe Li <ye.li@nxp.com>
Sun, 21 Feb 2021 16:26:23 +0000 (08:26 -0800)
committerStefano Babic <sbabic@denx.de>
Sat, 17 Jul 2021 11:12:23 +0000 (13:12 +0200)
Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
arch/arm/include/asm/arch-imx8m/clock.h
arch/arm/mach-imx/imx8m/clock_imx8mq.c

index 77d9428a188ac343afd5a0ad2cef94b4793a3d3d..c705dfdf460571d21ac3a50f8dd76f3911104520 100644 (file)
@@ -257,6 +257,7 @@ u32 imx_get_uartclk(void);
 int clock_init(void);
 void init_clk_usdhc(u32 index);
 void init_uart_clk(u32 index);
+void init_usb_clk(void);
 void init_wdog_clk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int clock_enable(enum clk_ccgr_index index, bool enable);
index 8fecc60ecb1c297c58bde907322869dcc037001a..60e2218a3ccc3fc7fac128fcfcd8e561a5dba028 100644 (file)
@@ -400,6 +400,28 @@ void init_wdog_clk(void)
        clock_enable(CCGR_WDOG3, 1);
 }
 
+void init_usb_clk(void)
+{
+       if (!is_usb_boot()) {
+               clock_enable(CCGR_USB_CTRL1, 0);
+               clock_enable(CCGR_USB_CTRL2, 0);
+               clock_enable(CCGR_USB_PHY1, 0);
+               clock_enable(CCGR_USB_PHY2, 0);
+               /* 500MHz */
+               clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
+                                    CLK_ROOT_SOURCE_SEL(1));
+               /* 100MHz */
+               clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+                                    CLK_ROOT_SOURCE_SEL(1));
+               /* 100MHz */
+               clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+                                    CLK_ROOT_SOURCE_SEL(1));
+               clock_enable(CCGR_USB_CTRL1, 1);
+               clock_enable(CCGR_USB_CTRL2, 1);
+               clock_enable(CCGR_USB_PHY1, 1);
+               clock_enable(CCGR_USB_PHY2, 1);
+       }
+}
 
 void init_nand_clk(void)
 {