x86: coreboot: Tell u-boot about PCI bus 0 when initializing

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 732ca3ceaff8fa8e01ed072ba0ea05a122dc947b..0ddc97501b7807ef72c322d0e88ab5e2bf4b9846 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -25,6 +25,21 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller coreboot_hose;
+
 void pci_init_board(void)
 {
+       coreboot_hose.first_busno = 0;
+       coreboot_hose.last_busno = 0xff;
+       coreboot_hose.region_count = 0;
+
+       pci_setup_type1(&coreboot_hose);
+
+       pci_register_hose(&coreboot_hose);
+
+       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
 }

diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 37cc7e3a0f849f59ed561a6ba44a319f00b0798e..6d68ab6c92623e38dfd591f89cf70ce5d888de19 100644 (file)
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -24,7 +24,7 @@
  */
 
 #ifndef _PCI_I386_H_
-#define _PCI_I386_H_   1
+#define _PCI_I386_H_
 
 #define DEFINE_PCI_DEVICE_TABLE(_table) \
        const struct pci_device_id _table[]