x86: coral: Support TPM and RTC in SPL

Update the devicetree so that the TPM and RTC can be used in SPL. Also
enable the pins used for getting the memory configuration settings while
we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 965f59276af646ea00f5d7a9a44b2e451550c23b..9319123c0c4f59b06b609c3510700756061d9cd1 100644 (file)
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/x86-gpio.h>
 
 /include/ "skeleton.dtsi"
@@ -99,6 +100,7 @@
        clk: clock {
                compatible = "intel,apl-clk";
                #clock-cells = <1>;
+               u-boot,dm-pre-reloc;
        };
 
        cpus {
@@ -139,6 +141,7 @@
        };
 
        acpi_gpe: general-purpose-events {
+               u-boot,dm-pre-reloc;
                reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
                compatible = "intel,acpi-gpe";
                interrupt-controller;
@@ -417,8 +420,10 @@
                };
 
                i2c_2: i2c2@16,2 {
-                       compatible = "intel,apl-i2c";
+                       compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
                        reg = <0x0200b210 0 0 0 0>;
+                       early-regs = <IOMAP_I2C2_BASE 0x1000>;
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        clock-frequency = <400000>;
@@ -429,6 +434,7 @@
                        tpm: tpm@50 {
                                reg = <0x50>;
                                compatible = "google,cr50";
+                               u-boot,dm-pre-reloc;
                                u-boot,i2c-offset-len = <0>;
                                ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
                                interrupts-extended = <&acpi_gpe GPIO_28_IRQ
@@ -583,6 +589,7 @@
                                u-boot,dm-pre-reloc;
                                cros_ec: cros-ec {
                                        u-boot,dm-pre-proper;
+                                       u-boot,dm-vpl;
                                        compatible = "google,cros-ec-lpc";
                                        reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -658,6 +665,11 @@
                PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
                PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
                PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
+
+               PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
+               PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
+               PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
+               PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
                >;
 };
 
@@ -1211,3 +1223,9 @@
                PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)       /* GP_CAMERASB11 */
        >;
 };
+
+&rtc {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
index 21c5f33021af2ab653cc7b400e9425a596ea5073..a4ea1507073597c2021e87e57a34861ca82335fb 100644 (file)
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -33,6 +33,9 @@
 #define SRAM_SIZE_2            (4 * KiB)
 #endif
 
+/* Early address for I2C port 2 */
+#define IOMAP_I2C2_BASE                (0xfe020000 + 2 * 0x1000)
+
 /*
  * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
  * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.