]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
board: terasic: Remove duplicate newlines
authorMarek Vasut <marek.vasut+renesas@mailbox.org>
Fri, 19 Jul 2024 10:49:09 +0000 (12:49 +0200)
committerTom Rini <trini@konsulko.com>
Mon, 22 Jul 2024 16:51:47 +0000 (10:51 -0600)
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
board/terasic/de1-soc/qts/iocsr_config.h
board/terasic/de1-soc/qts/pll_config.h
board/terasic/de10-nano/qts/iocsr_config.h
board/terasic/de10-nano/qts/pll_config.h
board/terasic/de10-standard/qts/iocsr_config.h
board/terasic/de10-standard/qts/pll_config.h
board/terasic/sockit/qts/iocsr_config.h
board/terasic/sockit/qts/pll_config.h

index 359fd0e4173b2a8abe25b83928616e54ddb08abe..46ef8288ed50bbf10266ccaf501f29b9a22f8829 100644 (file)
@@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00004000,
 };
 
-
 #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
index 2811e04c48076bbf619d513a2173cca1e5efac34..ae3cd316743f85ec04c71bc3df098698e92c4083 100644 (file)
@@ -86,5 +86,4 @@
 #define CFG_HPS_ALTERAGRP_MAINCLK 3
 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
-
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
index a889d3da348517a1cf486e40174d221913f11b57..155550007a3a90198f33217ce6eae19902f5bcdf 100644 (file)
@@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00004000,
 };
 
-
 #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
index 192ffb4e27b22c537827cee73bf1462be238a71d..794fa203d945f5ea20927d6cfdc1f43f64efa492 100644 (file)
@@ -80,5 +80,4 @@
 #define CFG_HPS_ALTERAGRP_MAINCLK 3
 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
-
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
index 4aed74e8b2986e1eeb2ff7b203b9e1d62da9ccad..80086b0c2938bdc8c67c483162e3ceee0928d7d0 100644 (file)
@@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00004000,
 };
 
-
 #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
index c1ecd4b8208f3b9846b2c46f7d3b93321409b616..b09b6adfab0b179f062ac9b6f1e5fbefee70552c 100644 (file)
@@ -80,5 +80,4 @@
 #define CFG_HPS_ALTERAGRP_MAINCLK 4
 #define CFG_HPS_ALTERAGRP_DBGATCLK 4
 
-
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
index 7b72ae9c3c2cb065b6920741def1c46a6d604c2f..8c247c8dfe57c927f973c89212f5dbfb8089cd68 100644 (file)
@@ -655,5 +655,4 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00004000,
 };
 
-
 #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
index 104e324d8a4fe23cdba9288f4b64ca34a1ebe5f8..52f1eb0c7b424364139aa74c51952e076f13e9d2 100644 (file)
@@ -80,5 +80,4 @@
 #define CFG_HPS_ALTERAGRP_MAINCLK 3
 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
-
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */