mpc83xx: Get rid of CONFIG_SYS_LBC_*

Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.

CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.

CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.

CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).

To simplify the configuration files, hardcode the setting of these
values for mpc83xx.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 090412d4b6c942de5f249134eacb8997d9de0919..c8e30a094784d8e0cfcdbdd676be99f45859ae1a 100644 (file)
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -109,8 +109,9 @@ int dram_init(void)
        msize = fixed_sdram();
 
        /* Local Bus setup lbcr and mrtpr */
-       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+       lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
+       /* LB refresh timer prescal, 266MHz/32 */
+       lbc->mrtpr = 0x20000000;
        sync();
 
 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index f14276f6a876fbe283b384e231b4a0ed954665d5..913b5843e9518ad457f53fc361a64a68c606e329 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -183,28 +183,36 @@ void sdram_init(void)
        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile fsl_lbc_t *lbc = &immap->im_lbc;
        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+       const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+                                LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+                                LSDMR_WRC3 | LSDMR_CL3;
        /*
         * Setup SDRAM Base and Option Registers, already done in cpu_init.c
         */
 
        /* setup mtrpt, lsrt and lbcr for LB bus */
-       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-       lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+       lbc->lbcr = 0x00000000;
+       /* LB refresh timer prescal, 266MHz/32 */
+       lbc->mrtpr = 0x20000000;
+       /* LB sdram refresh timer, about 6us */
+       lbc->lsrt = 0x32000000;
        asm("sync");
 
        /*
         * Configure the SDRAM controller Machine Mode Register.
         */
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+       /* 0x40636733; normal operation */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+       /* 0x68636733; precharge all the banks */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+       /* 0x48636733; auto refresh */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
        asm("sync");
        /*1 times*/
        *sdram_addr = 0xff;
@@ -232,12 +240,13 @@ void sdram_init(void)
        udelay(100);
 
        /* 0x58636733; mode register write operation */
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       /* 0x40636733; normal operation */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);

diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index a66234aa8578acf9d54848d53909236d8a442044..caa36064f053b467d2fe239edc64419aa0920802 100644 (file)
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -129,8 +129,8 @@ int dram_init(void)
 
        msize = setup_sdram();
 
-       out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-       out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+       out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
+       out_be32(&lbc->mrtpr, 0x20000000);
        sync();
 
        gd->ram_size = msize;

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index e51eeae065dfe165b0be8985b13e4eb07c391549..a647de6b11217b0b05aa6b2741566b19df8c4215 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -147,6 +147,9 @@ void sdram_init(void)
        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        volatile fsl_lbc_t *lbc = &immap->im_lbc;
        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+       const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+                                LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+                                LSDMR_WRC3 | LSDMR_CL3;
 
        puts("\n   SDRAM on Local Bus: ");
        print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@@ -156,22 +159,27 @@ void sdram_init(void)
         */
 
        /* setup mtrpt, lsrt and lbcr for LB bus */
-       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-       lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+       lbc->lbcr = 0x00000000;
+       /* LB refresh timer prescal, 266MHz/32 */
+       lbc->mrtpr = 0x20000000;
+       /* LB sdram refresh timer, about 6us */
+       lbc->lsrt = 0x32000000;
        asm("sync");
 
        /*
         * Configure the SDRAM controller Machine Mode Register.
         */
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       /* 0x40636733; normal operation */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+       /* 0x68636733; precharge all the banks */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+       /* 0x48636733; auto refresh */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
        asm("sync");
        /*1 times*/
        *sdram_addr = 0xff;
@@ -199,12 +207,13 @@ void sdram_init(void)
        udelay(100);
 
        /* 0x58636733; mode register write operation */
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);
 
-       lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       /* 0x40636733; normal operation */
+       lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
        asm("sync");
        *sdram_addr = 0xff;
        udelay(100);

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index f4148a21e3b0778a9d5c8d2654b6268075aa02b7..1559ff210daa3c6fd8e85e05df4a11efe1648bbf 100644 (file)
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -100,8 +100,8 @@ int dram_init(void)
        msize = fixed_sdram();
 
        /* Local Bus setup lbcr and mrtpr */
-       out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-       out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+       out_be32(&lbc->lbcr, 0x00040000);
+       out_be32(&lbc->mrtpr, 0x20000000);
        sync();
 
        /* return total bus SDRAM size(bytes)  -- DDR */

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 5d31d4a0b6b6188d615c7d2f19bf22ab6c444454..85d7ff6c521467240fd15c201ec012a6be12aa9c 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -121,11 +121,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 6f100fc7e7bcd2edbbbe091362c9d6d5a7f1def1..4153d609be4a49541a0e3fcb902798d802d34791 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -186,16 +186,6 @@
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)    /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (512 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR    (0x00040000 /* TODO */ \
-                               | (0xFF << LBCR_BMT_SHIFT) \
-                               | 0xF)  /* 0x0004ff0f */
-
-                               /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR   0x20000000  /*TODO */
-
 /* drivers/mtd/nand/raw/nand.c */
 #if defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_NAND_BASE           0xFFF00000

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 0f246dc5186587a249271829a91a50461cb87673..ff8dedf03e468537ed357c40b9207c3e9448785f 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -159,16 +159,6 @@
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)    /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (512 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR    (0x00040000 /* TODO */ \
-                               | (0xFF << LBCR_BMT_SHIFT) \
-                               | 0xF)  /* 0x0004ff0f */
-
-                               /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR   0x20000000  /*TODO */
-
 /* drivers/mtd/nand/nand.c */
 #define CONFIG_SYS_NAND_BASE           0xE2800000
 

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 0b94b0c5cf920ea28d15dc2e05b8ca8f12960c6d..521c5ca6eec5f3b1ac8e6bc2de0519814a9cd9d0 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -116,11 +116,7 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-#define CONFIG_FSL_ELBC                1
+#define CONFIG_FSL_ELBC
 
 /*
  * FLASH on the Local Bus

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index a90a9a86f8d62ebb6164590b9b75815ffdd4898a..418c6729e199c4495eb4d0baf6d15d19f7413238 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -113,11 +113,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00000000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 88b6f87397801ad7783c00af828c5731168a492e..df9cc48417f1cdb05ddc960d9c61029dc8a888a6 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -113,11 +113,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00000000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index fdbd15ea93eb0e4a47cb32e708f03f9e1590a466..7640d7610d670f14c9d6d0d9c5ca882b5c13a278 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -153,14 +153,6 @@
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)    /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 /*
  * Serial Port
  */

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 1e0e297351eefb1727efeeb12d213c76240247c5..493f6df187425850eb6b813bad9384ba2802dd06 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -150,14 +150,6 @@
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)    /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 /*
  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  */

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 388910ac38d54982b37ecde6c4f031cc2f0e64f7..a3f704c73b2346a2cd8066e2bdec38085b559daa 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -250,19 +250,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024) /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
-                               /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT    0x32000000
-                               /* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR   0x20000000
-
 /*
  * Serial Port
  */

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 61f9eaf71505fadbb1e34d15eb8077a0f048e71e..724f8afb76d16ec8c7a529d754fbe4156a3afab4 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -134,10 +134,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00000000
 #define CONFIG_FSL_ELBC                1
 
 /*

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 07b206ff9f950efb07310945d2490078d53d4a5f..13a768295855809f0f168757af95af93ac61ea63 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -158,10 +158,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00000000
 #define CONFIG_FSL_ELBC                1
 
 /*

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index 928136f325f666002b2446a8a279691198815003..15ac17985f39bf644503281ce3aedb0e41351bc6 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -96,14 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index d73e848b0c72c3238d101a36e0f91b84b5ef5a76..8029ae9dd7518fb048d62213f4c52977d06da97b 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -110,11 +110,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 155815a8815c5e8920be17a9d41bae679c679e5e..b1d01c58f977aa0db7c38162f1d60083f03431df 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -36,15 +36,6 @@
                                         - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR            (0x00040000 |\
-                                        (0xFF << LBCR_BMT_SHIFT) |\
-                                        0xF)
-
-#define CONFIG_SYS_LBC_MRTPR           0x20000000
-
 /*
  * Internal Definitions
  */

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index 0759604810a613694c7dfe578cee01683a5b51c7..0094f34ef1ba8915f353677d7810ba2cbc454d42 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 319e3bc1ece3bcbb2aa92f21111071bb17d4be8e..5afb969379bfad45320ee7b297adaeb7daad5c9b 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index 85e9101b054bfca5fa501436c7d5452ca8bbe33f..4f61ed0346d59cbcd9294575fdb47aa37894cc11 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -341,11 +341,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 6ec944f9429c123949a3a7a90e59d94674fccb98..862fdb7e2d7ef5c9373f4fff19fa707a2e7c4542 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index d7cbdde215d3495d98f44a375f1446ef6158d69d..802ab9c93447233ce3d7aab3ee30e49b3ef8968f 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -333,11 +333,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE           0xA0000000
 #define CONFIG_SYS_APP1_SIZE           256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE           0xB0000000

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 0392c3e8b40f21e284e78467c9471de5ed18d16f..3ce4b705b7073c034034fd9e0270de4d2cb0d95b 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -125,11 +125,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b4ae7b75543956a21b8f917153170e665c8ccdd7..d2053cc0597a8bf85f2f4c99766d77d636a6c5ea 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -123,14 +123,6 @@
 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)    /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*

diff --git a/include/configs/strider.h b/include/configs/strider.h
index e92bd1e8f105da82f7712ac8da94e370794d8e1f..22d255aabb869ed35f15e19fef55f0bdd5123506 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -110,11 +110,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 8b3b45416daf29607e5dd3031f3c4c59bde69eac..9421204f2c374169b27fbaa6ad9d1c6b9aac80a3 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -286,11 +286,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE           0xA0000000
 #define CONFIG_SYS_APP1_SIZE           256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE           0xB0000000

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 5dc9e8997e5af0730b704fcecc3109f08ac56ff2..3364b5379ea1576ed98bb444902b3a9ea54e7a6d 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index 9f8c855fb81807ec3dda968e410e3a2710555d79..db22fe50db0f086978932d943c6a2aba3b1dc47e 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #define CONFIG_SYS_APP1_BASE   0xA0000000    /* PAXG */
 #define        CONFIG_SYS_APP1_SIZE    256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE   0xB0000000    /* PINC3 */

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 2116d6bbcf8b8a4e3d84a2c592c1fa6e92728878..66f771d818f1fc5f71cf614edbae590f71b7687d 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -128,13 +128,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (384 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024)
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR    0x00040000
-
-#define CONFIG_SYS_LBC_MRTPR   0x20000000
-
 /*
  * NAND settings
  */

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 1bce6c732d99d1b3b67480caf7345dbb7eed63d7..1c3430d849183161bb56252d066b50751b8d29aa 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -96,14 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*