clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
}
-static void setup_dcemode_uart(void)
-{
- clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
- clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
-}
static void setup_iomux_dte_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
ARRAY_SIZE(uart1_pads_dte));
}
-static void setup_iomux_dce_uart(void)
-{
- setup_dcemode_uart();
- imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
- ARRAY_SIZE(uart1_pads_dce));
-}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
ARRAY_SIZE(pwr_intb_pads));
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
setup_iomux_dte_uart();
-#else
- setup_iomux_dce_uart();
-#endif
+
return 0;
}
rev = get_board_revision();
snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
env_set("board_rev", env_str);
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
- if ((rev & 0xfff0) == 0x0100) {
- char *fdt_env;
-
- /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
- setup_iomux_dce_uart();
-
- /* if using the default device tree, use version for V1.0 HW */
- fdt_env = env_get("fdt_file");
- if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
- env_set("fdt_file", FDT_FILE_V1_0);
- printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
- }
- }
-#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
-#endif /* CONFIG_REVISION_TAG */
+#endif /* CONFIG_BOARD_LATE_INIT */
#ifdef CONFIG_CMD_USB_SDP
if (is_boot_from_usb()) {
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
/* Make sure we use dte mode */
setup_dtemode_uart();
-#endif
/* DDR initialization */
spl_dram_init();