]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Correct SPL uses of SANDBOX_CLK_CCF
authorSimon Glass <sjg@chromium.org>
Sun, 5 Feb 2023 22:40:43 +0000 (15:40 -0700)
committerTom Rini <trini@konsulko.com>
Fri, 10 Feb 2023 12:41:40 +0000 (07:41 -0500)
This converts 12 usages of this option to the non-SPL form, since there is
no SPL_SANDBOX_CLK_CCF defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
drivers/clk/clk-divider.c
drivers/clk/clk-gate.c
drivers/clk/clk-mux.c
include/linux/clk-provider.h

index 7e8e62feeeeb27ae701ffbffe730155a1837534d..6ab137a72bef4b0086afea1c3e6047197accfbcd 100644 (file)
@@ -81,7 +81,7 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
        unsigned long parent_rate = clk_get_parent_rate(clk);
        unsigned int val;
 
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        val = divider->io_divider_val;
 #else
        val = readl(divider->reg);
@@ -210,7 +210,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
        div->width = width;
        div->flags = clk_divider_flags;
        div->table = table;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        div->io_divider_val = *(u32 *)reg;
 #endif
 
index aa40daf3d79c28b8742ac35dd47f82e1182178bb..a8775c77dc2e04cd151bda57fc370e61ace71cee 100644 (file)
@@ -62,7 +62,7 @@ static void clk_gate_endisable(struct clk *clk, int enable)
                if (set)
                        reg |= BIT(gate->bit_idx);
        } else {
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
                reg = gate->io_gate_val;
 #else
                reg = readl(gate->reg);
@@ -96,7 +96,7 @@ int clk_gate_is_enabled(struct clk *clk)
        struct clk_gate *gate = to_clk_gate(clk);
        u32 reg;
 
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        reg = gate->io_gate_val;
 #else
        reg = readl(gate->reg);
@@ -142,7 +142,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
        gate->reg = reg;
        gate->bit_idx = bit_idx;
        gate->flags = clk_gate_flags;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        gate->io_gate_val = *(u32 *)reg;
 #endif
 
index b49946fbcd58ec06f2c37326ca1576b5ae4e6a20..184d426d0b3cb23dc0fe77a2b22e2e6efc42a186 100644 (file)
@@ -90,7 +90,7 @@ u8 clk_mux_get_parent(struct clk *clk)
        struct clk_mux *mux = to_clk_mux(clk);
        u32 val;
 
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        val = mux->io_mux_val;
 #else
        val = readl(mux->reg);
@@ -137,7 +137,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
        if (mux->flags & CLK_MUX_HIWORD_MASK) {
                reg = mux->mask << (mux->shift + 16);
        } else {
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
                reg = mux->io_mux_val;
 #else
                reg = readl(mux->reg);
@@ -146,7 +146,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
        }
        val = val << mux->shift;
        reg |= val;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        mux->io_mux_val = reg;
 #else
        writel(reg, mux->reg);
@@ -194,7 +194,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
        mux->mask = mask;
        mux->flags = clk_mux_flags;
        mux->table = table;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        mux->io_mux_val = *(u32 *)reg;
 #endif
 
index 2d04882d05377525234938bc5e6099cdb84fb2d8..b8acacd49ee59195f7eb840572636a4214f547cb 100644 (file)
@@ -65,7 +65,7 @@ struct clk_mux {
         */
        const char      * const *parent_names;
        u8              num_parents;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        u32             io_mux_val;
 #endif
 
@@ -93,7 +93,7 @@ struct clk_gate {
        void __iomem    *reg;
        u8              bit_idx;
        u8              flags;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        u32             io_gate_val;
 #endif
 };
@@ -121,7 +121,7 @@ struct clk_divider {
        u8              width;
        u8              flags;
        const struct clk_div_table      *table;
-#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
        u32             io_divider_val;
 #endif
 };