dm: net: macb: Implement link speed change callback

At present the link speed change callback is a nop. According to
macb device tree bindings, an optional "tx_clk" is used to clock
the ethernet controller's TX_CLK under different link speed.

In 10/100 MII mode, transmit logic must be clocked from a free
running clock generated by the external PHY. In gigabit GMII mode,
the controller, not the external PHY, must generate the 125 MHz
transmit clock towards the PHY.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b7f404e857195fb57cfc8c82a88a6fe1d3c8c01d..c5560a71114f47767f7aaaf850ee67a235b1ad0b 100644 (file)
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -497,6 +497,41 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
 #ifdef CONFIG_DM_ETH
 int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
 {
+#ifdef CONFIG_CLK
+       struct clk tx_clk;
+       ulong rate;
+       int ret;
+
+       /*
+        * "tx_clk" is an optional clock source for MACB.
+        * Ignore if it does not exist in DT.
+        */
+       ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
+       if (ret)
+               return 0;
+
+       switch (speed) {
+       case _10BASET:
+               rate = 2500000;         /* 2.5 MHz */
+               break;
+       case _100BASET:
+               rate = 25000000;        /* 25 MHz */
+               break;
+       case _1000BASET:
+               rate = 125000000;       /* 125 MHz */
+               break;
+       default:
+               /* does not change anything */
+               return 0;
+       }
+
+       if (tx_clk.dev) {
+               ret = clk_set_rate(&tx_clk, rate);
+               if (ret)
+                       return ret;
+       }
+#endif
+
        return 0;
 }
 #else