tools: mtk_image: add support for nand headers used by newer chips

This patch adds more nand headers in two new types:
1. HSM header, used for spi-nand thru SNFI interface
2. SPIM header, used for spi-nand thru spi-mem interface

The original nand header is renamed to AP header.

Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 1f7396aa699b5e21238585fcc17b6adcb2aaffa2..9b3136afa3b1f3262b1e30fe41157b6571359cea 100644 (file)
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -33,6 +33,9 @@ static const struct brom_img_type {
        }, {
                .name = "snand",
                .type = BRLYT_TYPE_SNAND
+       }, {
+               .name = "spim-nand",
+               .type = BRLYT_TYPE_SNAND
        }
 };
 
@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot";
 static uint32_t crc32tbl[256];
 
 /* NAND header selected by user */
-static const union nand_boot_header *hdr_nand;
+static const struct nand_header_type *hdr_nand;
 static uint32_t hdr_nand_size;
 
 /* GFH header + 2 * 4KB pages of NAND */
@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr, int print)
        if (ret < 0)
                return ret;
 
-       bh = (struct brom_layout_header *)(ptr + info.page_size);
+       if (!ret) {
+               bh = (struct brom_layout_header *)(ptr + info.page_size);
 
-       if (strcmp(bh->name, BRLYT_NAME))
-               return -1;
+               if (strcmp(bh->name, BRLYT_NAME))
+                       return -1;
+
+               if (le32_to_cpu(bh->magic) != BRLYT_MAGIC)
+                       return -1;
 
-       if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) {
-               return -1;
-       } else {
                if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND)
                        bootmedia = "Parallel NAND";
                else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND)
                        bootmedia = "Serial NAND (SNFI/AP)";
                else
                        return -1;
+       } else {
+               if (info.snfi)
+                       bootmedia = "Serial NAND (SNFI/HSM)";
+               else
+                       bootmedia = "Serial NAND (SPIM)";
        }
 
        if (print) {

diff --git a/tools/mtk_nand_headers.c b/tools/mtk_nand_headers.c
index 12f827c39f7852fd1794fac871fe073fdcf75c66..2fa91e7af038e6e3aad0160464488450666e64df 100644 (file)
--- a/tools/mtk_nand_headers.c
+++ b/tools/mtk_nand_headers.c
@@ -188,55 +188,346 @@ static const union nand_boot_header nand_hdr_4gb_2k_128_data = {
        }
 };
 
-static const struct nand_header_type {
+/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */
+static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+               0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6,
+               0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62,
+               0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA,
+               0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51,
+               0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB,
+               0xED, 0x21, 0x02, 0x23, 0x51, 0x31
+       }
+};
+
+/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */
+static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+               0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC,
+               0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A,
+               0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81,
+               0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2,
+               0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24,
+               0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC
+       }
+};
+
+/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */
+static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+               0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F,
+               0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50,
+               0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2,
+               0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E,
+               0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9,
+               0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44
+       }
+};
+
+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */
+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+               0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA,
+               0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23,
+               0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D,
+               0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D,
+               0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E,
+               0x4E, 0x0E
+       }
+};
+
+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */
+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+               0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F,
+               0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B,
+               0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89,
+               0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49,
+               0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D,
+               0x8E, 0x53
+       }
+};
+
+/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */
+static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = {
+       .data = {
+               0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+               0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+               0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+               0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+               0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
+               0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE,
+               0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F,
+               0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24,
+               0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21,
+               0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88,
+               0x78, 0x6C
+       }
+};
+
+/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */
+static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = {
+       .data = {
+               0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30,
+               0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+       }
+};
+
+/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */
+static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = {
+       .data = {
+               0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
+               0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+               0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30,
+               0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+       }
+};
+
+/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */
+static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = {
+       .data = {
+               0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21,
+               0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
+               0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+               0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30,
+               0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+       }
+};
+
+struct nand_header_type {
        const char *name;
-       const union nand_boot_header *data;
+       enum nand_boot_header_type type;
+       union {
+               const union nand_boot_header *ap;
+               const union hsm_nand_boot_header *hsm;
+               const union hsm20_nand_boot_header *hsm20;
+               const union spim_nand_boot_header *spim;
+       };
 } nand_headers[] = {
        {
                .name = "2k+64",
-               .data = &snand_hdr_2k_64_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &snand_hdr_2k_64_data,
        }, {
                .name = "2k+120",
-               .data = &snand_hdr_2k_128_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &snand_hdr_2k_128_data,
        }, {
                .name = "2k+128",
-               .data = &snand_hdr_2k_128_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &snand_hdr_2k_128_data,
        }, {
                .name = "4k+256",
-               .data = &snand_hdr_4k_256_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &snand_hdr_4k_256_data,
        }, {
                .name = "1g:2k+64",
-               .data = &nand_hdr_1gb_2k_64_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &nand_hdr_1gb_2k_64_data,
        }, {
                .name = "2g:2k+64",
-               .data = &nand_hdr_2gb_2k_64_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &nand_hdr_2gb_2k_64_data,
        }, {
                .name = "4g:2k+64",
-               .data = &nand_hdr_4gb_2k_64_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &nand_hdr_4gb_2k_64_data,
        }, {
                .name = "2g:2k+128",
-               .data = &nand_hdr_2gb_2k_128_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &nand_hdr_2gb_2k_128_data,
        }, {
                .name = "4g:2k+128",
-               .data = &nand_hdr_4gb_2k_128_data
+               .type = NAND_BOOT_AP_HEADER,
+               .ap = &nand_hdr_4gb_2k_128_data,
+       }, {
+               .name = "hsm:2k+64",
+               .type = NAND_BOOT_HSM_HEADER,
+               .hsm = &hsm_nand_hdr_2k_64_data,
+       }, {
+               .name = "hsm:2k+128",
+               .type = NAND_BOOT_HSM_HEADER,
+               .hsm = &hsm_nand_hdr_2k_128_data,
+       }, {
+               .name = "hsm:4k+256",
+               .type = NAND_BOOT_HSM_HEADER,
+               .hsm = &hsm_nand_hdr_4k_256_data,
+       },  {
+               .name = "hsm20:2k+64",
+               .type = NAND_BOOT_HSM20_HEADER,
+               .hsm20 = &hsm20_nand_hdr_2k_64_data,
+       }, {
+               .name = "hsm20:2k+128",
+               .type = NAND_BOOT_HSM20_HEADER,
+               .hsm20 = &hsm20_nand_hdr_2k_128_data,
+       }, {
+               .name = "hsm20:4k+256",
+               .type = NAND_BOOT_HSM20_HEADER,
+               .hsm20 = &hsm20_nand_hdr_4k_256_data,
+       }, {
+               .name = "spim:2k+64",
+               .type = NAND_BOOT_SPIM_HEADER,
+               .spim = &spim_nand_hdr_2k_64_data,
+       }, {
+               .name = "spim:2k+128",
+               .type = NAND_BOOT_SPIM_HEADER,
+               .spim = &spim_nand_hdr_2k_128_data,
+       }, {
+               .name = "spim:4k+256",
+               .type = NAND_BOOT_SPIM_HEADER,
+               .spim = &spim_nand_hdr_4k_256_data,
        }
 };
 
-const union nand_boot_header *mtk_nand_header_find(const char *name)
+const struct nand_header_type *mtk_nand_header_find(const char *name)
 {
        uint32_t i;
 
        for (i = 0; i < ARRAY_SIZE(nand_headers); i++) {
                if (!strcmp(nand_headers[i].name, name))
-                       return nand_headers[i].data;
+                       return &nand_headers[i];
        }
 
        return NULL;
 }
 
-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand)
+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand)
 {
-       return 2 * le16_to_cpu(hdr_nand->pagesize);
+       switch (hdr_nand->type) {
+       case NAND_BOOT_HSM_HEADER:
+               return le32_to_cpu(hdr_nand->hsm->page_size);
+
+       case NAND_BOOT_HSM20_HEADER:
+               return le32_to_cpu(hdr_nand->hsm20->page_size);
+
+       case NAND_BOOT_SPIM_HEADER:
+               return le32_to_cpu(hdr_nand->spim->page_size);
+
+       default:
+               return 2 * le16_to_cpu(hdr_nand->ap->pagesize);
+       }
 }
 
 static int mtk_nand_header_ap_info(const void *ptr,
@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const void *ptr,
        info->page_size = le16_to_cpu(nh->pagesize);
        info->spare_size = le16_to_cpu(nh->oobsize);
        info->gfh_offset = 2 * info->page_size;
+       info->snfi = true;
 
        return 0;
 }
 
+static int mtk_nand_header_hsm_info(const void *ptr,
+                                   struct nand_header_info *info)
+{
+       union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr;
+
+       info->page_size = le16_to_cpu(nh->page_size);
+       info->spare_size = le16_to_cpu(nh->spare_size);
+       info->gfh_offset = info->page_size;
+       info->snfi = true;
+
+       return 1;
+}
+
+static int mtk_nand_header_spim_info(const void *ptr,
+                                    struct nand_header_info *info)
+{
+       union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr;
+
+       info->page_size = le16_to_cpu(nh->page_size);
+       info->spare_size = le16_to_cpu(nh->spare_size);
+       info->gfh_offset = info->page_size;
+       info->snfi = false;
+
+       return 1;
+}
+
 int mtk_nand_header_info(const void *ptr, struct nand_header_info *info)
 {
        if (!strcmp((char *)ptr, NAND_BOOT_NAME))
                return mtk_nand_header_ap_info(ptr, info);
+       else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8))
+               return mtk_nand_header_hsm_info(ptr, info);
+       else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8))
+               return mtk_nand_header_spim_info(ptr, info);
 
        return -1;
 }
@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr)
        return false;
 }
 
-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr)
+static uint16_t crc16(const uint8_t *p, uint32_t len)
+{
+       uint16_t crc = 0x4f4e;
+       uint32_t i;
+
+       while (len--) {
+               crc ^= *p++ << 8;
+               for (i = 0; i < 8; i++)
+                       crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+       }
+
+       return crc;
+}
+
+static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand,
+                                      void *ptr)
 {
-       union nand_boot_header *nh = (union nand_boot_header *)ptr;
        int i;
 
        /* NAND device header, repeat 4 times */
-       for (i = 0; i < 4; i++)
-               memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header));
+       for (i = 0; i < 4; i++) {
+               memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap));
+               ptr += sizeof(*hdr_nand->ap);
+       }
 
-       return le16_to_cpu(hdr_nand->pagesize);
+       return le16_to_cpu(hdr_nand->ap->pagesize);
+}
+
+static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand,
+                                       void *ptr)
+{
+       memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm));
+       return 0;
+}
+
+static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand,
+                                         void *ptr)
+{
+       memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20));
+       return 0;
+}
+
+static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand,
+                                        void *ptr)
+{
+       uint16_t crc;
+
+       memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim));
+
+       crc = crc16(ptr, 0x4e);
+       memcpy(ptr + 0x4e, &crc, sizeof(uint16_t));
+
+       return 0;
+}
+
+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr)
+{
+       switch (hdr_nand->type) {
+       case NAND_BOOT_HSM_HEADER:
+               return mtk_nand_header_put_hsm(hdr_nand, ptr);
+
+       case NAND_BOOT_HSM20_HEADER:
+               return mtk_nand_header_put_hsm20(hdr_nand, ptr);
+
+       case NAND_BOOT_SPIM_HEADER:
+               return mtk_nand_header_put_spim(hdr_nand, ptr);
+
+       default:
+               return mtk_nand_header_put_ap(hdr_nand, ptr);
+       }
 }

diff --git a/tools/mtk_nand_headers.h b/tools/mtk_nand_headers.h
index 20506cab38406122852f59032249c2da9c799890..9b1c4bab11692a1eaa593272ffd1ddc305d60914 100644 (file)
--- a/tools/mtk_nand_headers.h
+++ b/tools/mtk_nand_headers.h
@@ -16,6 +16,7 @@ struct nand_header_info {
        uint32_t page_size;
        uint32_t spare_size;
        uint32_t gfh_offset;
+       bool snfi;
 };
 
 /* AP BROM Header for NAND */
@@ -39,15 +40,117 @@ union nand_boot_header {
        uint8_t data[0x80];
 };
 
+/* HSM BROM Header for NAND */
+union hsm_nand_boot_header {
+       struct {
+               char id[8];
+               uint32_t version;               /* Header version */
+               uint32_t config;                /* Header config */
+               uint32_t sector_size;           /* ECC step size */
+               uint32_t fdm_size;              /* User OOB size of a step */
+               uint32_t fdm_ecc_size;          /* ECC parity size of a step */
+               uint32_t lbs;
+               uint32_t page_size;             /* NAND page size */
+               uint32_t spare_size;            /* NAND page spare size */
+               uint32_t page_per_block;        /* Pages of one block */
+               uint32_t blocks;                /* Total blocks of NAND chip */
+               uint32_t plane_sel_position;    /* Plane bit position */
+               uint32_t pll;                   /* Value of pll reg */
+               uint32_t acccon;                /* Value of access timing reg */
+               uint32_t strobe_sel;            /* Value of DQS selection reg*/
+               uint32_t acccon1;               /* Value of access timing reg */
+               uint32_t dqs_mux;               /* Value of DQS mux reg */
+               uint32_t dqs_ctrl;              /* Value of DQS control reg */
+               uint32_t delay_ctrl;            /* Value of delay ctrl reg */
+               uint32_t latch_lat;             /* Value of latch latency reg */
+               uint32_t sample_delay;          /* Value of sample delay reg */
+               uint32_t driving;               /* Value of driving reg */
+               uint32_t bl_start;              /* Bootloader start addr */
+               uint32_t bl_end;                /* Bootloader end addr */
+               uint8_t ecc_parity[42];         /* ECC parity of this header */
+       };
+
+       uint8_t data[0x8E];
+};
+
+/* HSM2.0 BROM Header for NAND */
+union hsm20_nand_boot_header {
+       struct {
+               char id[8];
+               uint32_t version;               /* Header version */
+               uint32_t config;                /* Header config */
+               uint32_t sector_size;           /* ECC step size */
+               uint32_t fdm_size;              /* User OOB size of a step */
+               uint32_t fdm_ecc_size;          /* ECC parity size of a step */
+               uint32_t lbs;
+               uint32_t page_size;             /* NAND page size */
+               uint32_t spare_size;            /* NAND page spare size */
+               uint32_t page_per_block;        /* Pages of one block */
+               uint32_t blocks;                /* Total blocks of NAND chip */
+               uint32_t plane_sel_position;    /* Plane bit position */
+               uint32_t pll;                   /* Value of pll reg */
+               uint32_t acccon;                /* Value of access timing reg */
+               uint32_t strobe_sel;            /* Value of DQS selection reg*/
+               uint32_t acccon1;               /* Value of access timing reg */
+               uint32_t dqs_mux;               /* Value of DQS mux reg */
+               uint32_t dqs_ctrl;              /* Value of DQS control reg */
+               uint32_t delay_ctrl;            /* Value of delay ctrl reg */
+               uint32_t latch_lat;             /* Value of latch latency reg */
+               uint32_t sample_delay;          /* Value of sample delay reg */
+               uint32_t driving;               /* Value of driving reg */
+               uint32_t reserved;
+               uint32_t bl0_start;             /* Bootloader start addr */
+               uint32_t bl0_end;               /* Bootloader end addr */
+               uint32_t bl0_type;              /* Bootloader type */
+               uint8_t bl_reserve[84];
+               uint8_t ecc_parity[42];         /* ECC parity of this header */
+       };
+
+       uint8_t data[0xEA];
+};
+
+/* SPIM BROM Header for SPI-NAND */
+union spim_nand_boot_header {
+       struct {
+               char id[8];
+               uint32_t version;               /* Header version */
+               uint32_t config;                /* Header config */
+               uint32_t page_size;             /* NAND page size */
+               uint32_t spare_size;            /* NAND page spare size */
+               uint16_t page_per_block;        /* Pages of one block */
+               uint16_t plane_sel_position;    /* Plane bit position */
+               uint16_t reserve_reg;
+               uint16_t reserve_val;
+               uint16_t ecc_error;             /* ECC error reg addr */
+               uint16_t ecc_mask;              /* ECC error bit mask */
+               uint32_t bl_start;              /* Bootloader start addr */
+               uint32_t bl_end;                /* Bootloader end addr */
+               uint8_t ecc_parity[32];         /* ECC parity of this header */
+               uint32_t integrity_crc;         /* CRC of this header */
+       };
+
+       uint8_t data[0x50];
+};
+
+enum nand_boot_header_type {
+       NAND_BOOT_AP_HEADER,
+       NAND_BOOT_HSM_HEADER,
+       NAND_BOOT_HSM20_HEADER,
+       NAND_BOOT_SPIM_HEADER
+};
+
 #define NAND_BOOT_NAME         "BOOTLOADER!"
 #define NAND_BOOT_VERSION      "V006"
 #define NAND_BOOT_ID           "NFIINFO"
 
+#define HSM_NAND_BOOT_NAME     "NANDCFG!"
+#define SPIM_NAND_BOOT_NAME    "SPINAND!"
+
 /* Find nand header data by name */
-const union nand_boot_header *mtk_nand_header_find(const char *name);
+const struct nand_header_type *mtk_nand_header_find(const char *name);
 
 /* Device header size using this nand header */
-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand);
+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand);
 
 /* Get nand info from nand header (page size, spare size, ...) */
 int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);
@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr, struct nand_header_info *info);
 bool is_mtk_nand_header(const void *ptr);
 
 /* Generate Device header using give nand header */
-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr);
+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand,
+                            void *ptr);
 
 #endif /* _MTK_NAND_HEADERS_H */