]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
colibri-imx6ull: imximage.cfg: integrate new 1GiB RAM variant
authorPhilippe Schenker <philippe.schenker@toradex.com>
Wed, 6 Oct 2021 16:55:35 +0000 (18:55 +0200)
committerStefano Babic <sbabic@denx.de>
Wed, 20 Oct 2021 15:49:59 +0000 (17:49 +0200)
Integrate new Toradex SKU 0062 Colibri iMX6ULL 1GB IT. This commit
basically adjusts three parameters of the RAM settings:

Increase density from 4Gb to 8Gb
Increase ROW address from 15 to 16
Increase tRFC (refresh command time) from 260 to 350

This timing is valid for all Toradex Colibri iMX6ULL SKUs

Related-to: ELB-4055, ELB-4057
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
board/toradex/colibri-imx6ull/imximage.cfg
include/configs/colibri-imx6ull.h

index 8d869d9f79e1adac2ed7d00c53939e0fe6f3800e..e162cff90f0ff693fc0c39c85e1a5f5c6dc994cc 100644 (file)
@@ -83,16 +83,14 @@ DATA 4 0x021B08C0 0x00944009
 DATA 4 0x021B08b8 0x00000800
 DATA 4 0x021B0004 0x0002002D
 DATA 4 0x021B0008 0x1B333030
-DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B000C 0x8B8F52F3
 DATA 4 0x021B0010 0xB66D0B63
 DATA 4 0x021B0014 0x01FF00DB
 DATA 4 0x021B0018 0x00201740
-DATA 4 0x021B001C 0x00008000
 DATA 4 0x021B002C 0x000026D2
-DATA 4 0x021B0030 0x006B1023
-DATA 4 0x021B0040 0x0000004F
-DATA 4 0x021B0000 0x84180000
-DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0030 0x008F1023
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0x85180000
 DATA 4 0x021B001C 0x02008032
 DATA 4 0x021B001C 0x00008033
 DATA 4 0x021B001C 0x00048031
@@ -100,7 +98,6 @@ DATA 4 0x021B001C 0x15208030
 DATA 4 0x021B001C 0x04008040
 DATA 4 0x021B0020 0x00000800
 DATA 4 0x021B0818 0x00000227
-DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0004 0x0002556D
 DATA 4 0x021B0404 0x00011006
 DATA 4 0x021B001C 0x00000000
-
index a2f2de7ea1c81acd0661b22703fd7d04c3255eda..85c855c098ba50b1b5977a8c9b76e3ef6f0dc685 100644 (file)
@@ -13,7 +13,7 @@
 #include "mx6_common.h"
 #define CONFIG_IOMUX_LPSR
 
-#define PHYS_SDRAM_SIZE                        SZ_512M
+#define PHYS_SDRAM_SIZE                        SZ_1G
 
 /* ENET1 */
 #define IMX_FEC_BASE                   ENET2_BASE_ADDR