arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0

The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3ca9b5c801f008c120badca09151797e72c8ab42..938e978a6b66a1cc68ec7977cd48cd72b8d5b6ca 100644 (file)
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -232,3 +232,13 @@
 &usb_serdes_mux {
        u-boot,mux-autoprobe;
 };
+
+&serdes0 {
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+};
+
+&serdes0_pcie_link {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+};

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4b2362a5dd059a0992e9073020a97657c3720e45..8299463c3e01b93159f8f0cfccdbe1cea4adc6b4 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
 #include "k3-j721e-som-p0.dtsi"
 #include "k3-j721e-ddr-evm-lp4-4266.dtsi"
 #include "k3-j721e-ddr.dtsi"
+#include <dt-bindings/phy/phy-cadence.h>
 
 / {
        aliases {
@@ -361,3 +362,26 @@
 &mcu_udmap {
        ti,sci = <&dm_tifs>;
 };
+
+&wiz0_pll1_refclk {
+       assigned-clocks = <&wiz0_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+       assigned-clocks = <&wiz0_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes0 {
+       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+       assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+       serdes0_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>;
+       };
+};