armv8: LS2080A: Consolidate LS2080A and LS2085A

LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index cce74052f7b8bb212a9088aa12dd3ba1a3c5ae13..5f86ef90d24e5e6941d70c1cead742dbe78d596a 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 endif
 
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
-endif
-
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 4b9e209054774f647c458f44485927b4f7eae14c..d93990036bc67802abc3274f22f03d82f34f3a58 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,12 +538,12 @@ int print_cpuinfo(void)
        struct sys_info sysinfo;
        char buf[32];
        unsigned int i, core;
-       u32 type, rcw;
+       u32 type, rcw, svr = gur_in32(&gur->svr);
 
        puts("SoC: ");
 
        cpu_name(buf);
-       printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+       printf(" %s (0x%x)\n", buf, svr);
        memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
        get_sys_info(&sysinfo);
        puts("Clock Configuration:");
@@ -564,7 +564,10 @@ int print_cpuinfo(void)
        printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+       if (soc_has_dp_ddr()) {
+               printf("     DP-DDR:   %-4s MT/s",
+                      strmhz(buf, sysinfo.freq_ddrbus2));
+       }
 #endif
        puts("\n");
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 81cf47049fb8eb67c6d3287f752b015a8647b7a6..d580a43b41254eac5c90a798a7d0feb8c29828d1 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info)
                        FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
                        FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
+       if (soc_has_dp_ddr()) {
+               sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
                        FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
                        FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+       } else {
+               sys_info->freq_ddrbus2 = 0;
+       }
 #endif
 
        for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 9c69ed13b47737c39c5f00b4cf952aacf63136a4..04831ca5bbc7611601d153f5a2d242398752fcf5 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -20,7 +20,7 @@ ENTRY(lowlevel_init)
 #ifdef CONFIG_FSL_LSCH3
 
        /* Set Wuo bit for RN-I 20 */
-#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
+#ifdef CONFIG_LS2080A
        ldr     x0, =CCI_AUX_CONTROL_BASE(20)
        ldr     x1, =0x00000010
        bl      ccn504_set_aux

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index a76447ec27bc9a64429c662698b5ff5378a5cd63..0cb010012e7add46e725741cbcb535e2bb9047f4 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -18,7 +18,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+bool soc_has_dp_ddr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 svr = gur_in32(&gur->svr);
+
+       /* LS2085A has DP_DDR */
+       if (SVR_SOC_VER(svr) == SVR_LS2085)
+               return true;
+
+       return false;
+}
+
+bool soc_has_aiop(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 svr = gur_in32(&gur->svr);
+
+       /* LS2085A has AIOP */
+       if (SVR_SOC_VER(svr) == SVR_LS2085)
+               return true;
+
+       return false;
+}
+
+#ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to
  * optimal the DDR performance.

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index f434c443ed5176940645f5edf7ac8c0479d8eebe..c1229c88af135f8cb465123719e07b5d4a4b353c 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -46,7 +46,7 @@ void board_init_f(ulong dummy)
 {
        /* Clear global data */
        memset((void *)gd, 0, sizeof(gd_t));
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
        arch_cpu_init();
 #endif
 #ifdef CONFIG_FSL_IFC
@@ -54,7 +54,7 @@ void board_init_f(ulong dummy)
 #endif
        board_early_init_f();
        timer_init();
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
        env_init();
 #endif
        get_clocks();

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ceefe431fdcbd6aa3a176bc3631338c62d4bb976..10d17b2bef082b7fec3a4d8049f75ef8857957d3 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -23,16 +23,11 @@
  */
 #define CONFIG_SYS_MEM_RESERVE_SECURE  (2048 * 1024)   /* 2MB */
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
-#ifdef CONFIG_LS2080A
-#define CONFIG_NUM_DDR_CONTROLLERS             2
-#endif
-#ifdef CONFIG_LS2085A
 #define CONFIG_NUM_DDR_CONTROLLERS             3
-#define CONFIG_SYS_FSL_HAS_DP_DDR
-#endif
+#define CONFIG_SYS_FSL_HAS_DP_DDR              /* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
 #define CONFIG_SYS_FSL_SRDS_1

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 905494232fa0cbfa0f87c063315f6822d80d8b87..702b9faabd9f23e11918008c929f80e821e3a884 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -206,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
          CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index d1fbde79d5176f42ffcff265b59340a18523cacf..f71c2c1773603da66181a74f09c1ea3dd8fa0f8b 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -9,7 +9,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 enum srds_prtcl {
        NONE = 0,
        PCIE1,

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 56989e1e08234848c2b20e0dde208bf585992a48..831d81764ec5d34e7c2b860fce999b901e4df7a6 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -94,4 +94,7 @@ void cpu_name(char *name);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
+
+bool soc_has_dp_ddr(void);
+bool soc_has_aiop(void);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index d576f2ef45a7f6cc252ffe4bb67939bf0dbe22af..53cd7550a0629e467e4f5153213a38c2cc4ec3eb 100644 (file)
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -44,15 +44,14 @@
 
 #endif
 
-#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
-       defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
- * Similiarly for LS2080 and LS2085
+ * Similiarly for LS2080
  */
 #define CONFIG_ESBC_ADDR_64BIT
 #endif
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_EXTRA_ENV \
        "setenv fdt_high 0xa0000000;"   \
        "setenv initrd_high 0xcfffffff;"        \
@@ -66,12 +65,11 @@
 
 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
  * Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
-       defined(CONFIG_LS2085A)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
 /* The address needs to be modified according to NOR and DDR memory map */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_BS_HDR_ADDR_FLASH       0x583920000
 #define CONFIG_BS_ADDR_FLASH           0x583900000
 #define CONFIG_BS_HDR_ADDR_RAM         0xa3920000

diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index 975ea2da48dbbc5382cd98d8067e68a7e257d33b..c8dac99889af3f941d7c3689291509e9a78126d5 100644 (file)
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -6,5 +6,3 @@ F:      include/configs/ls2080a_emu.h
 F:     configs/ls2080a_emu_defconfig
 F:     include/configs/ls2080a_simu.h
 F:     configs/ls2080a_simu_defconfig
-F:     configs/ls2085a_emu_defconfig
-F:     configs/ls2085a_simu_defconfig

diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 56c5d96e99d5914e14078d3aedfb8f5ba97ef828..1827ddca6952097fe726db7e9844f3884b1c143a 100644 (file)
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
        }
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-       /* initialize DP-DDR here */
-       puts("DP-DDR:  ");
-       /*
-        * DDR controller use 0 as the base address for binding.
-        * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-        */
-       dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+       if (soc_has_dp_ddr()) {
+               /* initialize DP-DDR here */
+               puts("DP-DDR:  ");
+               /*
+                * DDR controller use 0 as the base address for binding.
+                * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+                */
+               dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
                                          CONFIG_DP_DDR_CTRL,
                                          CONFIG_DP_DDR_NUM_CTRLS,
                                          CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
                                          NULL, NULL, NULL);
-       if (dp_ddr_size) {
-               gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-               gd->bd->bi_dram[2].size = dp_ddr_size;
-       } else {
-               puts("Not detected");
+               if (dp_ddr_size) {
+                       gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+                       gd->bd->bi_dram[2].size = dp_ddr_size;
+               } else {
+                       puts("Not detected");
+               }
        }
 #endif
 }

diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index ace0d795433c12f98cf565e23310b5f62849d199..00337d7091ccea032b16abad48f2ff34673d3685 100644 (file)
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -42,7 +42,7 @@ void detail_board_ddr_info(void)
        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
        print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       if (gd->bd->bi_dram[2].size) {
+       if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
                puts("\nDP-DDR ");
                print_size(gd->bd->bi_dram[2].size, "");
                print_ddr_info(CONFIG_DP_DDR_CTRL);

diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 558cef11905b50d4d38b63d07d3f29f90a9f7ac1..7d3bfc8e4eff5e8b1514b727ba921da035061fb4 100644 (file)
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -6,11 +6,8 @@ F:     board/freescale/ls2080a/ls2080aqds.c
 F:     include/configs/ls2080aqds.h
 F:     configs/ls2080aqds_defconfig
 F:     configs/ls2080aqds_nand_defconfig
-F:     configs/ls2085aqds_defconfig
-F:     configs/ls2085aqds_nand_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:     Saksham Jain <saksham.jain@nxp.freescale.com>
 S:     Maintained
 F:     configs/ls2080aqds_SECURE_BOOT_defconfig
-F:     configs/ls2085aqds_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 9fb5e112db00d0ff70f24448a718a26b83aadfd2..fcb03665bf97d83fe6e67de38acb5ba7afb67784 100644 (file)
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
        }
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-       /* initialize DP-DDR here */
-       puts("DP-DDR:  ");
-       /*
-        * DDR controller use 0 as the base address for binding.
-        * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-        */
-       dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+       if (soc_has_dp_ddr()) {
+               /* initialize DP-DDR here */
+               puts("DP-DDR:  ");
+               /*
+                * DDR controller use 0 as the base address for binding.
+                * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+                */
+               dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
                                          CONFIG_DP_DDR_CTRL,
                                          CONFIG_DP_DDR_NUM_CTRLS,
                                          CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
                                          NULL, NULL, NULL);
-       if (dp_ddr_size) {
-               gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-               gd->bd->bi_dram[2].size = dp_ddr_size;
-       } else {
-               puts("Not detected");
+               if (dp_ddr_size) {
+                       gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+                       gd->bd->bi_dram[2].size = dp_ddr_size;
+               } else {
+                       puts("Not detected");
+               }
        }
 #endif
 }

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index e1a521d0805c2aac5fa8d6faa3f2b0e333bf20bf..b3bd40afb77407d09c4a9f54d6b0428ad02ddbe3 100644 (file)
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -228,7 +228,7 @@ void detail_board_ddr_info(void)
        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
        print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       if (gd->bd->bi_dram[2].size) {
+       if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
                puts("\nDP-DDR ");
                print_size(gd->bd->bi_dram[2].size, "");
                print_ddr_info(CONFIG_DP_DDR_CTRL);

diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 0817711d089e9ba0f3bc8bea1ccfeb23dd69f4ae..5562917ec97715ace5ec30443ba312850c6a332f 100644 (file)
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -6,11 +6,8 @@ F:     board/freescale/ls2080a/ls2080ardb.c
 F:     include/configs/ls2080ardb.h
 F:     configs/ls2080ardb_defconfig
 F:     configs/ls2080ardb_nand_defconfig
-F:     configs/ls2085ardb_defconfig
-F:     configs/ls2085ardb_nand_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:     Saksham Jain <saksham.jain@nxp.freescale.com>
 S:     Maintained
 F:     configs/ls2080ardb_SECURE_BOOT_defconfig
-F:     configs/ls2085ardb_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index 6c191738ec4a013c8bad341b93ffc547dead0780..a04d21be130df2b234577f18dca099bab8328346 100644 (file)
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
        }
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-       /* initialize DP-DDR here */
-       puts("DP-DDR:  ");
-       /*
-        * DDR controller use 0 as the base address for binding.
-        * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-        */
-       dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+       if (soc_has_dp_ddr()) {
+               /* initialize DP-DDR here */
+               puts("DP-DDR:  ");
+               /*
+                * DDR controller use 0 as the base address for binding.
+                * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+                */
+               dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
                                          CONFIG_DP_DDR_CTRL,
                                          CONFIG_DP_DDR_NUM_CTRLS,
                                          CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
                                          NULL, NULL, NULL);
-       if (dp_ddr_size) {
-               gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-               gd->bd->bi_dram[2].size = dp_ddr_size;
-       } else {
-               puts("Not detected");
+               if (dp_ddr_size) {
+                       gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+                       gd->bd->bi_dram[2].size = dp_ddr_size;
+               } else {
+                       puts("Not detected");
+               }
        }
 #endif
 }

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 82010481934780e33f9b36602394987f8e7c5854..fb39af64452f6a2edd743da2839edc009e10e4a6 100644 (file)
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -207,7 +207,7 @@ void detail_board_ddr_info(void)
        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
        print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       if (gd->bd->bi_dram[2].size) {
+       if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
                puts("\nDP-DDR ");
                print_size(gd->bd->bi_dram[2].size, "");
                print_ddr_info(CONFIG_DP_DDR_CTRL);

diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig
deleted file mode 100644 (file)
index 036bb6f..0000000
--- a/configs/ls2085a_emu_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_EMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2085a_simu_defconfig
deleted file mode 100644 (file)
index 0702bab..0000000
--- a/configs/ls2085a_simu_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_SIMU=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig
deleted file mode 100644 (file)
index f13ee41..0000000
--- a/configs/ls2085aqds_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
-CONFIG_RSA=y

diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
deleted file mode 100644 (file)
index a5c8388..0000000
--- a/configs/ls2085aqds_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y

diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig
deleted file mode 100644 (file)
index d355c9a..0000000
--- a/configs/ls2085aqds_nand_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080AQDS=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/configs/ls2085ardb_SECURE_BOOT_defconfig b/configs/ls2085ardb_SECURE_BOOT_defconfig
deleted file mode 100644 (file)
index aa66508..0000000
--- a/configs/ls2085ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y
-CONFIG_RSA=y

diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig
deleted file mode 100644 (file)
index fe46dbc..0000000
--- a/configs/ls2085ardb_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_FSL_DSPI=y

diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig
deleted file mode 100644 (file)
index 5fb0cf6..0000000
--- a/configs/ls2085ardb_nand_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080ARDB=y
-CONFIG_SPL=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

diff --git a/doc/device-tree-bindings/serial/8250.txt b/doc/device-tree-bindings/serial/8250.txt
index 91d5ab0e60fc4eda6894ea94213bfb1ca8eb4572..ba8edae0ee34f0c005f20780e8e462fd7546476d 100644 (file)
--- a/doc/device-tree-bindings/serial/8250.txt
+++ b/doc/device-tree-bindings/serial/8250.txt
@@ -53,7 +53,7 @@ Note:
 
   Represents a single port that is compatible with the DUART found
   on many Freescale chips (examples include mpc8349, mpc8548,
-  mpc8641d, p4080 and ls2085a).
+  mpc8641d, p4080 and ls2080a).
 
 Example:
 

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 3fc418a8c42b142645cbffa29c470a6de868102e..8bc517dadcfd442f692500a9fadb114ca08e2d5f 100644 (file)
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -545,12 +545,12 @@ int sec_init(void)
 
        /*
         * Modifying CAAM Read/Write Attributes
-        * For LS2080A and LS2085A
+        * For LS2080A
         * For AXI Write - Cacheable, Write Back, Write allocate
         * For AXI Read - Cacheable, Read allocate
-        * Only For LS2080a and LS2085a, to solve CAAM coherency issues
+        * Only For LS2080a, to solve CAAM coherency issues
         */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
        mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
        mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
 #else

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index d2b8b5c47f15b757548a8b574e76f322b22e8da0..1811b0fe1a3f13d40203013bb4fb3a5a05c66b3e 100644 (file)
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -356,6 +356,12 @@ static unsigned long get_mc_boot_timeout_ms(void)
 }
 
 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+
+__weak bool soc_has_aiop(void)
+{
+       return false;
+}
+
 static int load_mc_aiop_img(u64 aiop_fw_addr)
 {
        u64 mc_ram_addr = mc_get_dram_addr();
@@ -363,6 +369,9 @@ static int load_mc_aiop_img(u64 aiop_fw_addr)
        void *aiop_img;
 #endif
 
+       /* Check if AIOP is available */
+       if (!soc_has_aiop())
+               return -ENODEV;
        /*
         * Load the MC AIOP image in the MC private DRAM block:
         */
@@ -1235,6 +1244,7 @@ static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                                aiop_fw_addr = simple_strtoull(argv[3], NULL,
                                                               16);
 
+                               /* if SoC doesn't have AIOP, err = -ENODEV */
                                err = load_mc_aiop_img(aiop_fw_addr);
                                if (!err)
                                        printf("fsl-mc: AIOP FW applied\n");

diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 74c49165d5fbe5978f1c0ded40b89d21f34e0413..5587aa618df554e11f91ecc14f8a6ae4d35215cb 100644 (file)
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -7,4 +7,3 @@
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
 obj-$(CONFIG_LS2080A) += ls2080a.o
-obj-$(CONFIG_LS2085A) += ls2080a.o

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 13ce349446d92f26744c2f99559c60628b7b4414..57e2a2919c1fd5be8744302c15c1c0c656a44d19 100644 (file)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -171,10 +171,9 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH            0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
-#ifdef CONFIG_LS2085A
+/* For LS2085A */
 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH   0x200000
 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET  0x07000000
-#endif
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -198,10 +197,6 @@ unsigned long long get_qixis_addr(void);
 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
 #endif
 
-#ifdef CONFIG_LS2085A
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
-#endif
-
 #define CONFIG_SYS_PCI_64BIT
 
 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000

diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index 534ebb6735dee5b099504d9de38da3b0b8276a13..f4ace856b87a338e4de1dcb2170e286f5bac9a68 100644 (file)
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -9,15 +9,8 @@
 
 #include "ls2080a_common.h"
 
-#ifdef CONFIG_LS2080A
 #define CONFIG_IDENT_STRING            " LS2080A-EMU"
 #define CONFIG_BOOTP_VCI_STRING                "U-Boot.LS2080A-EMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING            " LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING                "U-Boot.LS2085A-EMU"
-#endif
 
 #define CONFIG_SYS_CLK_FREQ    100000000
 #define CONFIG_DDR_CLK_FREQ    133333333

diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 2c2ce7bfecde216f718bd445d5b3147cbe88a8ef..0dbe95f406967d70fa851fa4d512de86439b0973 100644 (file)
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -9,15 +9,8 @@
 
 #include "ls2080a_common.h"
 
-#ifdef CONFIG_LS2080A
 #define CONFIG_IDENT_STRING            " LS2080A-SIMU"
 #define CONFIG_BOOTP_VCI_STRING                "U-Boot.LS2080A-SIMU"
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_IDENT_STRING            " LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING                "U-Boot.LS2085A-SIMU"
-#endif
 
 #define CONFIG_SYS_CLK_FREQ    100000000
 #define CONFIG_DDR_CLK_FREQ    133333333

diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index e922e322eb862e09ff16f843b808f12f09a0b359..c5e42e69fe2b3476487bd5c8d6cc73fab7fecb00 100644 (file)
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -55,7 +55,7 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#elif defined(CONFIG_LS2080A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0