#define DDR3_MR2_TWL(n) \
(((n - 5) & 0x7) << 3)
-
#ifdef CONFIG_TPL_BUILD
static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
-
/*
* The controller can represent tFAW as 4x, 5x or 6x tRRD only.
* We want to use the smallest multiplier that satisfies the tFAW
.get_info = rk3368_dmc_get_info,
};
-
static const struct udevice_id rk3368_dmc_ids[] = {
{ .compatible = "rockchip,rk3368-dmc" },
{ }
return -EINVAL;
}
-
params->bank_params[bank].sdram_timing =
(struct stm32_sdram_timing *)
ofnode_read_u8_array_ptr(bank_node,
return -EINVAL;
}
-
bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
bank++;