ARM: dts: rmobile: Sync Gen2 DTs with Linux 4.19.6

Synchronize DTs with mainline Linux 4.19.6 ,
commit 96db90800c06d3fe3fa08eb6222fe201286bb778

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master

diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts
index dcda98c6ae00782dc2f3a0ed09a748f2c29871c3..50312e752e2fae3dc42c6a0c6b45b78b0db7dcf1 100644 (file)
--- a/arch/arm/dts/r8a7790-lager.dts
+++ b/arch/arm/dts/r8a7790-lager.dts
@@ -899,9 +899,6 @@
        status = "okay";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin1ep0: endpoint {
                        remote-endpoint = <&adv7180>;
                        bus-width = <8>;
@@ -926,6 +923,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &ssi1 {
        shared-pin;
 };

diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index ed09e56c362bffaf7482d12548d2631fa790ead1..0925bdca438feedaa8ee956f8109fcca75dbbe1f 100644 (file)
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -76,12 +76,12 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1300000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1400000 1000000>,
@@ -101,6 +101,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu2: cpu@2 {
@@ -112,6 +122,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu3: cpu@3 {
@@ -123,6 +143,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu4: cpu@100 {
@@ -199,6 +229,24 @@
                clock-frequency = <0>;
        };
 
+       pmu-0 {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
+       pmu-1 {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -215,6 +263,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7790-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7790",
                                     "renesas,rcar-gen2-gpio";
@@ -440,7 +498,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 
@@ -1541,7 +1599,7 @@
                        interrupt-controller;
                        reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
                              <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
-                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&cpg CPG_MOD 408>;
                        clock-names = "clk";
                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1612,6 +1670,33 @@
                        resets = <&cpg 127>;
                };
 
+               fdp1@fe940000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe940000 0 0x2400>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 119>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 119>;
+               };
+
+               fdp1@fe944000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe944000 0 0x2400>;
+                       interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 118>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 118>;
+               };
+
+               fdp1@fe948000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe948000 0 0x2400>;
+                       interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 117>;
+                       power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                       resets = <&cpg 117>;
+               };
+
                jpu: jpeg-codec@fe980000 {
                        compatible = "renesas,jpu-r8a7790",
                                     "renesas,rcar-gen2-jpu";
@@ -1770,10 +1855,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
        /* External USB clock - can be overridden by the board */

diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts
index be96bfd4f36057c5f0ab19fa0fb398134bf0c274..ce22db01fbbaafb4689cc736cc357f8ec7f7f335 100644 (file)
--- a/arch/arm/dts/r8a7791-koelsch.dts
+++ b/arch/arm/dts/r8a7791-koelsch.dts
@@ -640,6 +640,11 @@
        status = "okay";
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &sata0 {
        status = "okay";
 };
@@ -847,9 +852,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin0ep2: endpoint {
                        remote-endpoint = <&adv7612_out>;
                        bus-width = <24>;
@@ -868,9 +870,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin1ep: endpoint {
                        remote-endpoint = <&adv7180>;
                        bus-width = <8>;

diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts
index f2d5723fbdc3cdd910b36bd241283039cab74cb0..f02036e5de015a95feec05c47ead06e91cb3daee 100644 (file)
--- a/arch/arm/dts/r8a7791-porter.dts
+++ b/arch/arm/dts/r8a7791-porter.dts
@@ -372,10 +372,43 @@
        clock-frequency = <400000>;
 };
 
+&i2c6 {
+       status = "okay";
+       clock-frequency = <100000>;
+
+       pmic@5a {
+               compatible = "dlg,da9063l";
+               reg = <0x5a>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+
+               wdt {
+                       compatible = "dlg,da9063-watchdog";
+               };
+       };
+
+       vdd_dvfs: regulator@68 {
+               compatible = "dlg,da9210";
+               reg = <0x68>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+               regulator-min-microvolt = <1000000>;
+               regulator-max-microvolt = <1000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+};
+
 &sata0 {
        status = "okay";
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_dvfs>;
+};
+
 /* composite video input */
 &vin0 {
        status = "okay";
@@ -383,9 +416,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin0ep: endpoint {
                        remote-endpoint = <&adv7180>;
                        bus-width = <8>;
@@ -478,6 +508,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &ssi1 {
        shared-pin;
 };

diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index d728738ba8682e5005595b9dba9c72193687b544..991ac6feedd5beb6123f7a12f98c8799d89f9565 100644 (file)
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -75,11 +75,11 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -98,6 +98,16 @@
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
                        power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
                };
 
                L2_CA15: cache-controller-0 {
@@ -123,6 +133,13 @@
                clock-frequency = <0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -139,6 +156,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7791-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7791",
                                     "renesas,rcar-gen2-gpio";
@@ -404,7 +431,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 
@@ -1618,6 +1645,24 @@
                        resets = <&cpg 127>;
                };
 
+               fdp1@fe940000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe940000 0 0x2400>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 119>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 119>;
+               };
+
+               fdp1@fe944000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe944000 0 0x2400>;
+                       interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 118>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 118>;
+               };
+
                jpu: jpeg-codec@fe980000 {
                        compatible = "renesas,jpu-r8a7791",
                                     "renesas,rcar-gen2-jpu";

diff --git a/arch/arm/dts/r8a7792-blanche.dts b/arch/arm/dts/r8a7792-blanche.dts
index 023d870bed88e5a2d90b7bb03cea5cb796f1564e..f92301290b026fdbb9d223b9da6907c7b06b6bd9 100644 (file)
--- a/arch/arm/dts/r8a7792-blanche.dts
+++ b/arch/arm/dts/r8a7792-blanche.dts
@@ -236,6 +236,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";

diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi
index 8e26dede308b2c252408559f49d1cc246346b4bb..63a978ec81cc09f0a4d989fff7171d893ba07387 100644 (file)
--- a/arch/arm/dts/r8a7792.dtsi
+++ b/arch/arm/dts/r8a7792.dtsi
@@ -82,6 +82,13 @@
                clock-frequency = <0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -98,6 +105,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7792-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7792",
                                     "renesas,rcar-gen2-gpio";
@@ -338,7 +355,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 

diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts
index 9c893458ce7d2179cc84f6ea086e0a951741f150..6b2f3a4fd13d646c35e48fc46a7efa31ab42035e 100644 (file)
--- a/arch/arm/dts/r8a7793-gose.dts
+++ b/arch/arm/dts/r8a7793-gose.dts
@@ -596,6 +596,11 @@
        status = "okay";
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &scif0 {
        pinctrl-0 = <&scif0_pins>;
        pinctrl-names = "default";
@@ -755,9 +760,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin0ep2: endpoint {
                        remote-endpoint = <&adv7612_out>;
                        bus-width = <24>;
@@ -777,9 +779,6 @@
        status = "okay";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin1ep: endpoint {
                        remote-endpoint = <&adv7180_out>;
                        bus-width = <8>;

diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi
index 8201b4e8d1df4d24edb8221196621ca7282702a1..620a570307ffcffa0ac2cc42918684882952b4b2 100644 (file)
--- a/arch/arm/dts/r8a7793.dtsi
+++ b/arch/arm/dts/r8a7793.dtsi
@@ -67,10 +67,10 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -89,6 +89,17 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
                        power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
+                       next-level-cache = <&L2_CA15>;
                };
 
                L2_CA15: cache-controller-0 {
@@ -107,6 +118,13 @@
                clock-frequency = <0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -123,6 +141,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7793-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7793",
                                     "renesas,rcar-gen2-gpio";
@@ -389,7 +417,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 
@@ -1287,6 +1315,24 @@
                        resets = <&cpg 408>;
                };
 
+               fdp1@fe940000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe940000 0 0x2400>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 119>;
+                       power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                       resets = <&cpg 119>;
+               };
+
+               fdp1@fe944000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe944000 0 0x2400>;
+                       interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 118>;
+                       power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                       resets = <&cpg 118>;
+               };
+
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7793";
                        reg = <0 0xfeb00000 0 0x40000>;

diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts
index af3c67eb02dedbc1ba01a809ff82a7b8272cc595..ef7e2a837df6da79596339e15bd0db2000fd27c5 100644 (file)
--- a/arch/arm/dts/r8a7794-alt.dts
+++ b/arch/arm/dts/r8a7794-alt.dts
@@ -178,6 +178,12 @@
                                };
                        };
                };
+
+               eeprom@50 {
+                       compatible = "renesas,r1ex24002", "atmel,24c02";
+                       reg = <0x50>;
+                       pagesize = <16>;
+               };
        };
 
        /*
@@ -327,6 +333,11 @@
        status = "okay";
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &sdhi0 {
        pinctrl-0 = <&sdhi0_pins>;
        pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -372,9 +383,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin0ep: endpoint {
                        remote-endpoint = <&adv7180>;
                        bus-width = <8>;

diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts
index 50dad43c102d1484e1375a6a1cf88429d9c6d11a..daec965889d3e5fe18e764daaf77758e24aacd0c 100644 (file)
--- a/arch/arm/dts/r8a7794-silk.dts
+++ b/arch/arm/dts/r8a7794-silk.dts
@@ -472,9 +472,6 @@
        pinctrl-names = "default";
 
        port {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
                vin0ep: endpoint {
                        remote-endpoint = <&adv7180>;
                        bus-width = <8>;
@@ -537,6 +534,11 @@
        };
 };
 
+&rwdt {
+       timeout-sec = <60>;
+       status = "okay";
+};
+
 &ssi1 {
        shared-pin;
 };

diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
index 0cc07b30d17df42ddf9065298a41837ec2307c14..ea2ca4bdaf1c129c3932644a45bce1145ebabfb6 100644 (file)
--- a/arch/arm/dts/r8a7794.dtsi
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -100,6 +100,13 @@
                clock-frequency = <0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -116,6 +123,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7794-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7794",
                                     "renesas,rcar-gen2-gpio";
@@ -345,7 +362,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 
@@ -1320,6 +1337,15 @@
                        resets = <&cpg 128>;
                };
 
+               fdp1@fe940000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe940000 0 0x2400>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 119>;
+                       power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                       resets = <&cpg 119>;
+               };
+
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7794";
                        reg = <0 0xfeb00000 0 0x40000>;