imx: mx6ull: update clock settings and CCM register map

Update Clock settings and CCM register map for i.MX6ULL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 9beb6f0193f42a9759bde12f2a4a3029c0041a7c..ae3143c760716906ac8f660114967c43ec0ce2c6 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -97,7 +97,10 @@ void enable_enet_clk(unsigned char enable)
 {
        u32 mask, *addr;
 
-       if (is_mx6ul()) {
+       if (is_mx6ull()) {
+               mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
+               addr = &imx_ccm->CCGR0;
+       } else if (is_mx6ul()) {
                mask = MXC_CCM_CCGR3_ENET_MASK;
                addr = &imx_ccm->CCGR3;
        } else {
@@ -117,7 +120,7 @@ void enable_uart_clk(unsigned char enable)
 {
        u32 mask;
 
-       if (is_mx6ul())
+       if (is_mx6ul() || is_mx6ull())
                mask = MXC_CCM_CCGR5_UART_MASK;
        else
                mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +171,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               if (is_mx6sx() || is_mx6ul()) {
+               if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
                } else {
@@ -279,7 +282,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
        switch (pll) {
        case PLL_BUS:
-               if (!is_mx6ul()) {
+               if (!is_mx6ul() && !is_mx6ull()) {
                        if (pfd_num == 3) {
                                /* No PFD3 on PLL2 */
                                return 0;
@@ -380,7 +383,7 @@ static u32 get_ipg_per_clk(void)
 
        reg = __raw_readl(&imx_ccm->cscmr1);
        if (is_mx6sl() || is_mx6sx() ||
-           is_mx6dqp() || is_mx6ul()) {
+           is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
                if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                        return MXC_HCLK; /* OSC 24Mhz */
        }
@@ -396,7 +399,8 @@ static u32 get_uart_clk(void)
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
 
-       if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
+       if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
+           is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                        freq = MXC_HCLK;
        }
@@ -415,7 +419,8 @@ static u32 get_cspi_clk(void)
        cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
                     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
+       if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
+           is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
                        return MXC_HCLK / (cspi_podf + 1);
        }
@@ -477,7 +482,7 @@ static u32 get_mmdc_ch0_clk(void)
 
        u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-       if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
+       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
                podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
                        MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
                if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -615,7 +620,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
        debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-       if (!is_mx6sx() && !is_mx6ul()) {
+       if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
                debug("This chip not support lcd!\n");
                return;
        }
@@ -749,7 +754,7 @@ int enable_lcdif_clock(u32 base_addr)
                         MXC_CCM_CCGR3_DISP_AXI_MASK) :
                        (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
                         MXC_CCM_CCGR3_DISP_AXI_MASK);
-       } else if (is_mx6ul()) {
+       } else if (is_mx6ul() || is_mx6ull()) {
                if (base_addr != LCDIF1_BASE_ADDR) {
                        puts("Wrong LCD interface!\n");
                        return -EINVAL;
@@ -847,7 +852,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
                reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
        } else if (fec_id == 1) {
                /* Only i.MX6SX/UL support ENET2 */
-               if (!(is_mx6sx() || is_mx6ul()))
+               if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
                        return -EINVAL;
                reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
                reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1069,17 +1074,27 @@ void hab_caam_clock_enable(unsigned char enable)
 {
        u32 reg;
 
-       /* CG4 ~ CG6, CAAM clocks */
-       reg = __raw_readl(&imx_ccm->CCGR0);
-       if (enable)
-               reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-       else
-               reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-       __raw_writel(reg, &imx_ccm->CCGR0);
+       if (is_mx6ull()) {
+               /* CG5, DCP clock */
+               reg = __raw_readl(&imx_ccm->CCGR0);
+               if (enable)
+                       reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
+               else
+                       reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
+               __raw_writel(reg, &imx_ccm->CCGR0);
+       } else {
+               /* CG4 ~ CG6, CAAM clocks */
+               reg = __raw_readl(&imx_ccm->CCGR0);
+               if (enable)
+                       reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                               MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                               MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+               else
+                       reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                               MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                               MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+               __raw_writel(reg, &imx_ccm->CCGR0);
+       }
 
        /* EMI slow clk */
        reg = __raw_readl(&imx_ccm->CCGR6);

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 22212c2202ea399edbdffdc12e7c3b409ba5403c..7a55aecb7fdf8753e81e32eb831ad8ec7481abd2 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -379,6 +379,16 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << 6)
 
 /* Define the bits in register CS1CDR */
+/* MX6UL, !MX6ULL */
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK              (0x7 << 22)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET            22
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK              (0x3F << 16)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET            16
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET            6
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK              0x3F
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET            0
+
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK              (0x3F << 25)
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET            25
 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK              (0x7 << 22)
@@ -460,7 +470,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
 
 /* Define the bits in register CHSCCDR */
-#ifdef CONFIG_MX6SX
+/* i.MX6SX */
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK          (0x7 << 15)
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET                15
 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                 (0x7 << 12)
@@ -473,7 +483,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET                 3
 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                        (0x7)
 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET              0
-#else
+
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK      (0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET    15
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK             (0x7 << 12)
@@ -486,7 +496,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET           3
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK          (0x7)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET                0
-#endif
+
+/* i.MX6ULL */
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK          (0x7 << 15)
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET                15
+#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK                 (0x7 << 12)
+#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET               12
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK              (0x7 << 9)
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET            9
 
 #define CHSCCDR_CLK_SEL_LDB_DI0                                3
 #define CHSCCDR_PODF_DIVIDE_BY_3                       2
@@ -626,6 +643,12 @@ struct mxc_ccm_reg {
 /* Define the bits in registers CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           3
 
+/* i.MX 6ULL */
+#define MXC_CCM_CCGR0_DCP_CLK_OFFSET           10
+#define MXC_CCM_CCGR0_DCP_CLK_MASK             (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET   12
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK     (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
+
 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                  0
 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                  2
@@ -702,13 +725,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_CANFD_MASK                       (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 #endif
 
-#ifndef CONFIG_MX6SX
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
-#else
+/* i.MX6SX/UL */
 #define MXC_CCM_CCGR2_CSI_OFFSET                       2
 #define MXC_CCM_CCGR2_CSI_MASK                         (3 << MXC_CCM_CCGR2_CSI_OFFSET)
-#endif
+
 #ifndef CONFIG_MX6SX
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
@@ -744,9 +766,18 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET        26
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 
+/* i.MX6ULL */
+#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET          0
+#define MXC_CCM_CCGR2_ESAI_CLK_MASK            (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET   4
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK     (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
+
 /* Exist on i.MX6SX */
 #define MXC_CCM_CCGR3_M4_OFFSET                                        2
 #define MXC_CCM_CCGR3_M4_MASK                                  (3 << MXC_CCM_CCGR3_M4_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET                   4
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK                     (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET                              4
 #define MXC_CCM_CCGR3_ENET_MASK                                        (3 << MXC_CCM_CCGR3_ENET_OFFSET)
 #define MXC_CCM_CCGR3_QSPI_OFFSET                              14
@@ -808,7 +839,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
 #define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 
-/* GPIO4 on i.MX6UL */
+/* GPIO4 on i.MX6UL/ULL */
 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET                         30
 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK                           (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
 
@@ -817,6 +848,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif
 
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET               30
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK                 (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
+
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
 #define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 /* QSPI2 on i.MX6SX */
@@ -883,6 +918,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_USDHC1_MASK              (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 #define MXC_CCM_CCGR6_USDHC2_OFFSET            4
 #define MXC_CCM_CCGR6_USDHC2_MASK              (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET          6
+#define MXC_CCM_CCGR6_SIM1_CLK_MASK            (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
+#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET          8
+#define MXC_CCM_CCGR6_SIM2_CLK_MASK            (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET                8
+#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK          (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
 /* GPMI/BCH on i.MX6UL */
 #define MXC_CCM_CCGR6_BCH_OFFSET               6
 #define MXC_CCM_CCGR6_BCH_MASK                 (3 << MXC_CCM_CCGR6_BCH_OFFSET)
@@ -895,6 +937,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_USDHC4_MASK              (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET          10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK            (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET      18
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK                (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
 /* The following *CCGR6* exist only i.MX6SX */
 #define MXC_CCM_CCGR6_PWM8_OFFSET              16
 #define MXC_CCM_CCGR6_PWM8_MASK                        (3 << MXC_CCM_CCGR6_PWM8_OFFSET)