arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4

Add support for i2c0, i2c1, i2c2, i2c3 and i2c4.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>

diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index db019599904e8d2a717b73dd957606911ca72bd5..af060db3a12864c8a6323167266bb9da3c341db7 100644 (file)
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -29,6 +29,11 @@
                mmc0 = &usdhc1;
                mmc1 = &usdhc2;
                mmc2 = &usdhc3;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
        };
 
        memory@80000000 {
@@ -224,6 +229,76 @@
                };
        };
 
+       i2c0: i2c@5a800000 {
+               compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x0 0x5a800000 0x0 0x4000>;
+               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_I2C0_CLK>,
+                        <&clk IMX8QM_I2C0_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_lpi2c0>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@5a810000 {
+               compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x0 0x5a810000 0x0 0x4000>;
+               interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_I2C1_CLK>,
+                        <&clk IMX8QM_I2C1_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_lpi2c1>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@5a820000 {
+               compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x0 0x5a820000 0x0 0x4000>;
+               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_I2C2_CLK>,
+                        <&clk IMX8QM_I2C2_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_lpi2c2>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@5a830000 {
+               compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x0 0x5a830000 0x0 0x4000>;
+               interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_I2C3_CLK>,
+                        <&clk IMX8QM_I2C3_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_lpi2c3>;
+               status = "disabled";
+       };
+
+       i2c4: i2c@5a840000 {
+               compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+               reg = <0x0 0x5a840000 0x0 0x4000>;
+               interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QM_I2C4_CLK>,
+                        <&clk IMX8QM_I2C4_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_lpi2c4>;
+               status = "disabled";
+       };
+
        gpio0: gpio@5d080000 {
                compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
                reg = <0x0 0x5d080000 0x0 0x10000>;