net: phy: dp83867: Clean force link good bit

On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 08935d9c15fccb8be842d4b1bbf2e0cbf24ae0fe..0098997c0cd9bf0f349c07b5145473328d5e9b5f 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -65,6 +65,7 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT         14
 #define DP83867_PHYCR_FIFO_DEPTH_MASK          GENMASK(15, 14)
 #define DP83867_PHYCR_RESERVED_MASK    BIT(11)
+#define DP83867_PHYCR_FORCE_LINK_GOOD  BIT(10)
 #define DP83867_MDI_CROSSOVER          5
 #define DP83867_MDI_CROSSOVER_MDIX     2
 #define DP83867_PHYCTRL_SGMIIEN                        0x0800
@@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev)
                val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
                val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 
+               /* Do not force link good */
+               val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
+
                /* The code below checks if "port mirroring" N/A MODE4 has been
                 * enabled during power on bootstrap.
                 *