ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3

Clean up odd multiline loop, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 16d09c12645f85f2937772b32ea40f1c8afe7a43..3d975f99fb76ce0ddf5e5bd082e7a2d837235f42 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1633,8 +1633,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
        }
 
        /* The dtap increment to find the failing edge is done here. */
-       for (; d <= IO_DQS_EN_DELAY_MAX;
-            d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+       for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
                debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
                           __func__, __LINE__, d);
 
@@ -1645,6 +1644,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
                                                              &bit_chk, 0)) {
                        break;
                }
+
+               work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
        }
 
        /* Go back to working dtap */